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cy7c6601 3 cy7c6611 3 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-08024 rev. *a revised march 6, 2003 full-speed usb (12 mbps) peripheral controller with integrated hub
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 2 of 58 table of contents 1.0 features .................................................................................................................. .................... 6 2.0 functional overview ....................................................................................................... ....... 7 2.1 gpio ...................................................................................................................... ..................... 7 2.2 dac ....................................................................................................................... ..................... 7 2.3 clock ..................................................................................................................... ...................... 7 2.4 memory .................................................................................................................... ................... 7 2.5 power-on reset, watchdog, and free-running time ................................................................. 7 2.6 i2c and hapi interface .................................................................................................... ........... 7 2.7 timer ..................................................................................................................... ...................... 7 2.8 interrupts ................................................................................................................ ..................... 8 2.9 usb ....................................................................................................................... ...................... 8 3.0 pin configurations ........................................................................................................ ........ 10 4.0 product summary tables ................................................................................................... 1 1 4.1 pin assignments ........................................................................................................... ............ 11 4.2 i/o register summary ...................................................................................................... ........ 11 4.3 instruction set summary ................................................................................................... ........13 5.0 programming model ......................................................................................................... ..... 14 5.1 14-bit program counter (pc) ............................................................................................... ..... 14 5.1.1 program memory organization ........................................................................................... .......... 15 5.2 8-bit accumulator (a) ..................................................................................................... ........... 16 5.3 8-bit temporary register (x) .............................................................................................. ...... 16 5.4 8-bit program stack pointer (psp) ......................................................................................... .. 16 5.4.1 data memory organization ................................................................................................ ............. 16 5.5 8-bit data stack pointer (dsp) ............................................................................................ ..... 16 5.6 address modes ............................................................................................................. ............ 17 5.6.1 data (immediate) ........................................................................................................ .................... 17 5.6.2 direct .................................................................................................................. ............................. 17 5.6.3 indexed ................................................................................................................. .......................... 17 6.0 clocking .................................................................................................................. ................... 17 7.0 reset ..................................................................................................................... ....................... 18 7.1 power-on reset ............................................................................................................ ............ 18 7.2 watchdog reset ............................................................................................................ ........... 18 8.0 suspend mode .............................................................................................................. ............. 19 9.0 general-purpose i/o (gpio) ports .................................................................................... 19 9.1 gpio configuration port ................................................................................................... ........20 9.2 gpio interrupt enable ports ............................................................................................... ...... 21 10.0 dac port ................................................................................................................. .................. 22 10.1 dac isink registers ...................................................................................................... .......... 23 10.2 dac port interrupts ...................................................................................................... ........... 23 11.0 12-bit free-running timer ................................................................................................ .. 24 12.0 i 2 c and hapi configuration register ............................................................................ 24 13.0 i 2 c-compatible controller .............................................................................................. 25 14.0 hardware assisted parallel interface (hapi) ........................................................ 27 15.0 processor status and control register ................................................................ 28
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 3 of 58 table of contents (continued) 16.0 interrupts ............................................................................................................... ................ 29 16.1 interrupt vectors ........................................................................................................ ............. 30 16.2 interrupt latency ........................................................................................................ ............. 31 16.3 usb bus reset interrupt .................................................................................................. ....... 31 16.4 timer interrupt .......................................................................................................... .............. 31 16.5 usb endpoint interrupts .................................................................................................. ....... 32 16.6 usb hub interrupt ........................................................................................................ ........... 32 16.7 dac interrupt ............................................................................................................ .............. 32 16.8 gpio/hapi interrupt ...................................................................................................... ......... 32 16.9 i 2 c interrupt ................................................................................................................... .......... 33 17.0 usb overview ............................................................................................................. ............. 33 17.1 usb serial interface engine .............................................................................................. ..... 33 17.2 usb enumeration .......................................................................................................... ......... 33 18.0 usb hub .................................................................................................................. ................... 34 18.1 connecting/disconnecting a usb device ............................................................................... 34 18.2 enabling/disabling a usb device .......................................................................................... .35 18.3 hub downstream ports status and control ............................................................................ 35 18.4 downstream port suspend and resume ................................................................................ 37 18.5 usb upstream port status and control .................................................................................. 38 19.0 usb sie operation ........................................................................................................ ......... 39 19.1 usb device addresses ..................................................................................................... ...... 39 19.2 usb device endpoints ..................................................................................................... ....... 39 19.3 usb control endpoint mode registers ................................................................................... 40 19.4 usb non-control endpoint mode registers ........................................................................... 41 19.5 usb endpoint counter registers ........................................................................................... 41 19.6 endpoint mode/count registers update and locking mechanism ......................................... 42 20.0 usb mode tables .......................................................................................................... ......... 44 21.0 register summary ......................................................................................................... ....... 48 22.0 sample schematic ......................................................................................................... ....... 51 23.0 absolute maximum ratings .............................................................................................. 52 24.0 electrical characteristics ............................................................................................ 52 25.0 switching characteristics (f osc = 6.0 mhz) ...................................................................................... 53 26.0 ordering information ..................................................................................................... ... 55 27.0 package diagrams ......................................................................................................... ...... 56
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 4 of 58 list of figures figure 5-1. program memory space with interrupt vector table ......................................................... 15 figure 6-1. clock oscillator on-chip circuit .................................................................................. ....... 17 figure 7-1. watchdog reset .................................................................................................... ............. 18 figure 9-1. block diagram of a gpio pin ....................................................................................... ...... 19 figure 9-2. port 0 data ....................................................................................................... .................. 20 figure 9-3. port1 data ........................................................................................................ .................. 20 figure 9-4. port 2 data ....................................................................................................... .................. 20 figure 9-5. port 3 data ....................................................................................................... .................. 20 figure 9-6. gpio configuration register ....................................................................................... ....... 20 figure 9-7. port 0 interrupt enable ........................................................................................... ............ 21 figure 9-8. port 1 interrupt enable ........................................................................................... ............ 22 figure 9-9. port 2 interrupt enable ........................................................................................... ............ 22 figure 9-10. port 3 interrupt enable .......................................................................................... ........... 22 figure 10-1. block diagram of a dac pin ....................................................................................... ..... 22 figure 10-2. dac port data .................................................................................................... .............. 23 figure 10-3. dac sink register ................................................................................................ ........... 23 figure 10-4. dac port interrupt enable ........................................................................................ ........ 23 figure 10-5. dac port interrupt polarity ...................................................................................... ......... 23 figure 11-3. timer block diagram .............................................................................................. .......... 24 figure 11-1. timer lsb register ............................................................................................... ........... 24 figure 11-2. timer msb register ............................................................................................... .......... 24 figure 12-1. hapi/i 2 c configuration register ...................................................................................... 24 figure 13-1. i 2 c data register .............................................................................................................. 2 5 figure 13-2. i 2 c status and control register ....................................................................................... 25 figure 15-1. processor status and control register ............................................................................ 28 figure 16-1. global interrupt enable register ................................................................................. ..... 29 figure 16-2. usb endpoint interrupt enable register .......................................................................... 2 9 figure 16-3. interrupt controller function diagram ............................................................................ .. 30 figure 16-4. gpio interrupt structure ......................................................................................... ......... 32 figure 18-1. hub ports connect status ......................................................................................... ....... 34 figure 18-2. hub ports speed .................................................................................................. ............ 35 figure 18-3. hub ports enable register ........................................................................................ ....... 35 figure 18-4. hub downstream ports control register ......................................................................... 36 figure 18-5. hub ports force low register ..................................................................................... .... 36 figure 18-6. hub ports force low register ..................................................................................... .... 36 figure 18-7. hub ports se0 status register .................................................................................... .... 36 figure 18-8. hub ports data register .......................................................................................... ........ 37 figure 18-9. hub ports suspend register ....................................................................................... ..... 37 figure 18-10. hub ports resume status register ............................................................................... 3 7 figure 18-11. usb status and control register ................................................................................. .. 38 figure 19-1. usb device address registers ..................................................................................... ... 39 figure 19-2. usb device endpoint zero mode registers .................................................................... 40 figure 19-3. usb non-control device endpoint mode registers ........................................................ 41 figure 19-4. usb endpoint counter registers ................................................................................... .. 41 figure 19-5. token/data packet flow diagram ................................................................................... .43 figure 22-1. sample schematic ................................................................................................. .......... 51 figure 25-1. clock timing ..................................................................................................... ................ 54 figure 25-2. usb data signal timing ........................................................................................... ........ 54 figure 25-3. hapi read by external interface from usb microcontroller ............................................ 54 figure 25-4. hapi write by external device to usb microcontroller .................................................... 55
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 5 of 58 list of tables table 4-1. pin assignments .................................................................................................... .............. 11 table 4-2. i/o register summary ............................................................................................... .......... 11 table 4-3. instruction set summary ............................................................................................ ......... 13 table 9-1. gpio port output control truth table and interrupt polarity .............................................. 21 table 12-1. hapi port configuration ........................................................................................... ......... 25 table 12-2. i 2 c port configuration ........................................................................................................ 25 table 13-1. i 2 c status and control register bit definitions .................................................................. 26 table 14-1. port 2 pin and hapi configuration bit definitions ............................................................. 27 table 16-1. interrupt vector assignments ...................................................................................... ...... 31 table 18-1. control bit definition for downstream ports ...................................................................... 3 6 table 18-2. control bit definition for upstream port .......................................................................... .. 39 table 19-1. memory allocation for endpoints ................................................................................. .... 40 table 20-1. usb register mode encoding ........................................................................................ ... 44 table 20-2. decode table for table 20-3 : ?details of modes for differing traffic conditions? ............. 45 table 20-3. details of modes for differing traffic conditions (see table 20-2 for the decode legend) 46
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 6 of 58 1.0 features ? full-speed usb peripheral microcontroller with an integrated usb hub ? well-suited for usb compound devices such as a keyboard hub function 8-bit usb optimized microcontroller ? harvard architecture ? 6-mhz external clock source ? 12-mhz internal cpu clock ? 48-mhz internal hub clock internal memory ? 256 bytes of ram ? 8 kb of prom (cy7c66013, cy7c66113) integrated master/slave i 2 c-compatible controller (100 khz) enabled through general-purpose i/o (gpio) pins hardware-assisted parallel interface (hapi) for data transfer to external devices i/o ports ? three gpio ports (port 0 to 2) capable of sinking 8 ma per pin (typical) ? an additional gpio port (port 3) capable of sinking 12 ma per pin (typical) for high current requirements: leds ? higher current drive achievable by connecting multiple gpio pins together to drive a common output ? each gpio port can be configured as inputs with internal pull-ups or open drain outputs or traditional cmos outputs ? a digital-to-analog conversion (dac) port with programmable current sink outputs is available on the cy7c66113 device ? maskable interrupts on all i/o pins 12-bit free-running timer with one microsecond clock ticks watchdog timer (wdt) internal power-on reset (por) usb specification compliance ? conforms to usb specification, version 1.1 ? conforms to usb hid specification, version 1.1 ? supports one or two device addresses wi th up to five user-configured endpoints up to two 8-byte control endpoints up to four 8-byte data endpoints up to two 32-byte data endpoints ? integrated usb transceivers ? supports four downstream usb ports ? gpio pins can provide individual power control outputs for each downstream usb port ? gpio pins can provide individual port over current inputs for each downstream usb port improved output drivers to reduce electromagnetic interference (emi) operating voltage from 4.0v ? 5.5v dc operating temperature from 0 ? 70 c cy7c66013 available in 48-pin pdip (-pc) or 48-pin ssop (-pvc) packages cy7c66113 available in 56-pin ssop (-pvc) packages industry-standard programmer support
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 7 of 58 2.0 functional overview the cy7c66013 and cy7c66113 are compound devices with a full-speed usb microcontroller in combination with a usb hub. each device is well-suited for combination peripheral functions with hubs, such as a keyboard hub function. the eight-bit one-time-programmable microcontroller with a 12-mbps usb hub supports as many as four downstream ports. 2.1 gpio the cy7c66013 features 29 gpio pins to support usb and other ap plications. the i/o pins are grouped into four ports (p0[7:0], p1[7:0], p2[7:0], p3[4:0]) where each port can be configured as inputs with internal pull-ups, open drain outputs, or tradition al cmos outputs. ports 0 to 2 are rated at 8 ma per pin (typical) sink current. port 3 pins are rated at 12 ma per pin (typical) s ink current, which allows these pins to drive leds. multiple gpio pins can be connected together to drive a single output for more drive current capacity. additionally, each i/o pin can be used to generate a gpio interrupt to the microcontroller. all of the gpio interrupts all share the same ?gpio? interrupt vector. the cy7c66113 has 31 gpio pins (p0[7:0], p1[7:0], p2[7:0], p3[6:0]). 2.2 dac the cy7c66113 have an additional port p4[7:0] that features an additional eight programmable sink current i/o pins (dac). every dac pin includes an integrated 14-k ? pull-up resistor. when a ?1? is written to a dac i/o pin, the output current sink is disabled and the output pin is driven high by the internal pull-up resistor. when a ?0? is written to a dac i/o pin, the intern al pull-up is disabled and the output pin provides the programmed amount of sink current. a dac i/o pin can be used as an input with an internal pull-up by writing a ?1? to the pin. the sink current for each dac i/o pin can be individually programmed to one of sixteen values using dedicated isink registers. dac bits dac[1:0] can be used as high current outputs with a programmable sink current range of 3.2 to 16 ma (typical). dac bits dac[7:2] have a programmable current sink range of 0.2 to 1.0 ma (typical). multiple dac pins can be connected together to drive a single output that requires more sink current capacity. each i/o pin can be used to generate a dac interrupt to the microcontroller. also, the interrupt polarity for each dac i/o pin is individually programmable. 2.3 clock the microcontroller uses an external 6-mhz crystal and an internal oscillator to provide a reference to an internal pll-based clock generator. this technology allows the customer application to use an inexpensive 6-mhz fundamental crystal that reduces the clock-related noise emissions (emi). a pll clock generator provides the 6-, 12-, and 48-mhz clock signals for distribution within the microcontroller. 2.4 memory the cy7c66013 and cy7c66113 have 8 kb of prom. 2.5 power-on reset, watchdog, and free-running time these parts include por logic, a wdt, and a 12-bit free-running timer. the por logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at prom address 0x0000. the wdt is used to ensure that the microcontroller recovers after a period of inactivity. the firmware may become inactive for a variety of reasons, incl uding errors in the code or a hardware failure such as waiting for an interrupt that never occurs. 2.6 i 2 c and hapi interface the microcontroller can communicate with external electronics through the gpio pins. an i 2 c-compatible interface accommo- dates a 100-khz serial link with an external device. there is also a hardware-assisted parallel interface (hapi) which can be used to transfer data to an external device. 2.7 timer the free-running 12-bit timer clocked at 1 mhz provides two interrupt sources, 128- s and 1.024-ms. the timer can be used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. the difference between the two readings indicates the duration of the event in microseconds. the upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. a read from the upper four bits a ctually reads data from the internal register, instead of the timer. this feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read.
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 8 of 58 2.8 interrupts the microcontroller supports eleven maskable interrupts in the vectored interrupt controller. interrupt sources include the 128 - s (bit 6) and 1.024-ms (bit 9) outputs from the free-running timer, five usb endpoints, the usb hub, the dac port, the gpio ports , and the i 2 c-compatible master mode interface. the timer bits cause an interrupt (if enabled) when the bit toggles from low ?0? to high ?1.? the usb endpoints interrupt after the usb host has written data to the endpoint fifo or after the usb controller sends a packet to the usb host. the dac ports have an additional level of masking that allows the user to select which dac inputs can cause a dac interrupt. the gpio ports also have a level of masking to select which gpio inputs can cause a gpio interrupt. for additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of t he dac port. input transition polarity can be programmed for each gpio port as part of the port configuration. the interrupt polarity can be rising edge (?0? to ?1?) or falling edge (?1? to ?0?). 2.9 usb the cy7c66013 and cy7c66113 include an integrated usb serial interface engine (sie) that supports the integrated periph- erals and the hub controller function. the hardware supports up to two usb device addresses with one device address for the hub (two endpoints) and a device address for a compound device (three endpoints). the sie allows the usb host to communicate with the hub and functions integrated into the microcontroller. the part includes a 1:4 hub repeater with one upstream port and four downstream ports. the usb hub allows power-management control of the downstream ports by using gpio pins assigned by the user firmware. the user has the option of ganging the downstream ports together with a single pair of power-management pins, or providing power management for each port with four pairs of power-management pins.
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 9 of 58 logic block diagram interrupt controller prom 12-bit timer reset watchdog timer repeater power-on sclk i 2 c usb transceiver usb transceiver usb transceiver gpio port 1 gpio port 0 p0[0] p0[7] p1[0] p1[7] sdata d+[3] d?[3] d+[2] d?[2] 8-bit bus 6-mhz crystal ram usb sie usb transceiver d+[4] d?[4] usb transceiver d+[0] d?[0] d+[1] d?[1] upstream usb port downstream usb ports gpio port 3 p3[0] p3[4] dac port dac[0] dac[7] high current outputs cy7c66113 only 256 byte 8 kb clock 6 mhz 12-mhz 8-bit cpu *i 2 c-compatible interface enabled by firmware through power management under firmware control using gpio pins interface gpio port 3 p3[5] p3[6] additional outputs high current pll 12 mhz 48 mhz divider gpio/ port 2 p2[0:1,7] p2[3]; data_ready p2[4]; stb p2[5]; oe p2[6]; cs p2[2]; latch_empty hapi p2[1:0] or p1[1:0]
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 10 of 58 3.0 pin configurations 1 2 3 4 5 6 7 9 11 12 13 14 15 16 18 17 xtalin 10 8 19 20 39 38 37 41 40 43 42 45 44 47 46 49 48 51 50 53 52 54 56 55 21 22 23 24 25 26 28 27 29 31 30 33 32 35 34 36 v cc p1[1] p1[0] p1[2] p1[4] p1[6] p3[0] d?[3] v ref p1[3] p1[5] p1[7] p3[1] d+[0] d?[0] p3[3] gnd p3[5] d+[1] d?[1] p2[1] d+[2] d?[2] p2[3] p2[5] p2[7] dac[7] p0[7] p0[5] p0[3] p0[1] dac[5] dac[3] dac[1] xtalout d+[3] p3[2] p3[4] d?[4] d+[4] p3[6] p2[0] p2[2] gnd p2[4] p2[6] dac[0] v pp p0[0] p0[2] p0[4] p0[6] dac[2] dac[4] dac[6] cy7c66113 56-pin ssop cy7c66013 1 2 3 4 5 6 7 9 11 12 13 14 15 16 18 17 xtalin 10 8 19 20 31 30 29 33 32 35 34 37 36 39 38 41 40 43 42 45 44 46 48 47 21 22 23 24 25 27 26 28 v cc p1[1] p1[0] p1[2] p1[4] p1[6] p3[0] d?[3] v ref p1[3] p1[5] p1[7] p3[1] d+[0] d?[0] p3[3] gnd d+[1] d?[1] p2[1] d+[2] d?[2] p2[3] p2[5] p2[7] gnd p0[7] p0[5] p0[3] p0[1] xtalout d+[3] p3[2] gnd p3[4] d?[4] d+[4] p2[0] p2[2] gnd p2[4] p2[6] v pp p0[0] p0[2] p0[4] p0[6] 48-pin pdip/ssop top view
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 11 of 58 4.0 product summary tables 4.1 pin assignments 4.2 i/o register summary i/o registers are accessed via the i/o read (iord) and i/o write (iowr, iowx) instructions. iord reads data from the selected port into the accumulator. iowr performs the reverse; it writes data from the accumulator to the selected port. indexed i/o wri te (iowx) adds the contents of x to the address in the instruction to form the port address and writes data from the accumulator t o the specified port. specifying address 0 (e.g., iowx 0h) means the i/o register is selected solely by the contents of x. all undefined registers are reserved. it is important not to write to reserved registers as this may cause an undefined operati on or increased current consumption during operation. when writing to registers with reserved bits, the reserved bits must be writ ten with ?0.? table 4-1. pin assignments name i/o 48-pin 56-pin description d+[0], d?[0] i/o 8, 9 8, 9 upstream port, usb differential data . d+[1], d?[1] i/o 12, 13 13, 14 downstream port 1, usb differential data . d+[2], d?[2] i/o 15, 16 16, 17 downstream port 2, usb differential data . d+[3], d?[3] i/o 40, 41 48, 49 downstream port 3, usb differential data . d+[4], d?[4] i/o 35, 36 44, 45 downstream port 4, usb differential data . p0[7:0] i/o 21, 25, 22, 26, 23, 27, 24, 28 22, 32, 23, 33, 24, 34, 25, 35 gpio port 0 . p1[7:0] i/o 6, 43, 5, 44, 4, 45, 47, 46 6, 51, 5, 52, 4, 53, 55, 54 gpio port 1 . p2[7:0] i/o 19, 30, 18, 31, 17, 33, 14, 34 20, 38, 19, 39, 18, 41, 15, 42 gpio port 2 . p3[6:0] i/o 37, 10, 39, 7, 42 43, 12, 46, 10, 47, 7, 50 gpio port 3, capable of sinking 12 ma (typical) . dac[7:0] i/o n/a 21, 29, 26, 30, 27, 31, 28, 37 digital to analog converter (dac) port with programmable current sink outputs. dac[1:0] offer a programmable range of 3.2 to 16 ma typical. dac[7:2] have a programmable sink current range of 0.2 to 1.0 ma typical. xtal in in 2 2 6-mhz crystal or external clock input . xtal out out 1 1 6-mhz crystal out . v pp 29 36 programming voltage supply, tie to ground during normal operation . v cc 48 56 voltage supply . gnd 11, 20, 32, 38 11, 40 ground . v ref in 3 3 external 3.3v supply voltage for the differential data output buffers and the d+ pull-up . table 4-2. i/o register summary register name i/o address read/write function page port 0 data 0x00 r/w gpio port 0 data 20 port 1 data 0x01 r/w gpio port 1 data 20 port 2 data 0x02 r/w gpio port 2 data 20 port 3 data 0x03 r/w gpio port 3 data 20 port 0 interrupt enable 0x04 w interrupt enable for pins in port 0 21 port 1 interrupt enable 0x05 w interrupt enable for pins in port 1 22 port 2 interrupt enable 0x06 w interrupt enable for pins in port 2 22 port 3 interrupt enable 0x07 w interrupt enable for pins in port 3 22 gpio configuration 0x08 r/w gpio port configurations 20
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 12 of 58 hapi and i 2 c configuration 0x09 r/w hapi width and i 2 c position configuration 24 usb device address a 0x10 r/w usb device address a 39 ep a0 counter register 0x11 r/w usb address a, endpoint 0 counter 41 ep a0 mode register 0x12 r/w usb address a, endpoint 0 configuration 40 ep a1 counter register 0x13 r/w usb address a, endpoint 1 counter 41 ep a1 mode register 0x14 r/w usb address a, endpoint 1 configuration 41 ep a2 counter register 0x15 r/w usb address a, endpoint 2 counter 41 ep a2 mode register 0x16 r/w usb address a, endpoint 2 configuration 41 usb status & control 0x1f r/w usb upstream port traffic status and control 38 global interrupt enable 0x20 r/w global interrupt enable 29 endpoint interrupt enable 0x21 r/w usb endpoint interrupt enables 29 interrupt vector 0x23 r pending interrupt vector read/clear 31 timer (lsb) 0x24 r lower 8 bits of free-running timer (1 mhz) 24 timer (msb) 0x25 r upper 4 bits of free-running timer 24 wdt clear 0x26 w watchdog timer clear 18 i 2 c control & status 0x28 r/w i 2 c status and control 25 i 2 c data 0x29 r/w i 2 c data 25 dac data 0x30 r/w dac data 23 dac interrupt enable 0x31 w interrupt enable for each dac pin 23 dac interrupt polarity 0x32 w interrupt polarity for each dac pin 23 dac isink 0x38-0x3f w input sink current control for each dac pin 23 usb device address b 0x40 r/w usb device address b (not used in 5-endpoint mode) 39 ep b0 counter register 0x41 r/w usb address b, endpoint 0 counter 41 ep b0 mode register 0x42 r/w usb address b, endpoint 0 configuration, or usb address a, endpoint 3 in 5-endpoint mode 40 ep b1 counter register 0x43 r/w usb address b, endpoint 1 counter 41 ep b1 mode register 0x44 r/w usb address b, endpoint 1 configuration, or usb address a, endpoint 4 in 5-endpoint mode 41 hub port connect status 0x48 r/w hub downstream port connect status 34 hub port enable 0x49 r/w hub downstream ports enable 35 hub port speed 0x4a r/w hub downstream ports speed 35 hub port control (ports [4:1]) 0x4b r/w hub downstream ports control 36 hub port suspend 0x4d r/w hub downstream port suspend control 37 hub port resume status 0x4e r hub downstream ports resume status 37 hub ports se0 status 0x4f r hub downstream ports se0 status 36 hub ports data 0x50 r hub downstream ports differential data 37 hub downstream force low 0x51 r/w hub downstream ports force low 36 processor status & control 0xff r/w microprocessor status and control register 28 table 4-2. i/o register summary (continued) register name i/o address read/write function page
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 13 of 58 4.3 instruction set summary refer to the cyasm assembler user?s guide for more details. table 4-3. instruction set summary mnemonic operand opcode cycles mnemonic operand opcode cycles halt 00 7 nop 20 4 add a,expr data 01 4 inc a acc 21 4 add a,[expr] direct 02 6 inc x x 22 4 add a,[x+expr] index 03 7 inc [expr] direct 23 7 adc a,expr data 04 4 inc [x+expr] index 24 8 adc a,[expr] direct 05 6 dec a acc 25 4 adc a,[x+expr] index 06 7 dec x x 26 4 sub a,expr data 07 4 dec [expr] direct 27 7 sub a,[expr] direct 08 6 dec [x+expr] index 28 8 sub a,[x+expr] index 09 7 iord expr address 29 5 sbb a,expr data 0a 4 iowr expr address 2a 5 sbb a,[expr] direct 0b 6 pop a 2b 4 sbb a,[x+expr] index 0c 7 pop x 2c 4 or a,expr data 0d 4 push a 2d 5 or a,[expr] direct 0e 6 push x 2e 5 or a,[x+expr] index 0f 7 swap a,x 2f 5 and a,expr data 10 4 swap a,dsp 30 5 and a,[expr] direct 11 6 mov [expr],a direct 31 5 and a,[x+expr] index 12 7 mov [x+expr],a index 32 6 xor a,expr data 13 4 or [expr],a direct 33 7 xor a,[expr] direct 14 6 or [x+expr],a index 34 8 xor a,[x+expr] index 15 7 and [expr],a direct 35 7 cmp a,expr data 16 5 and [x+expr],a index 36 8 cmp a,[expr] direct 17 7 xor [expr],a direct 37 7 cmp a,[x+expr] index 18 8 xor [x+expr],a index 38 8 mov a,expr data 19 4 iowx [x+expr] index 39 6 mov a,[expr] direct 1a 5 cpl 3a 4 mov a,[x+expr] index 1b 6 asl 3b 4 mov x,expr data 1c 4 asr 3c 4 mov x,[expr] direct 1d 5 rlc 3d 4 reserved 1e rrc 3e 4 xpage 1f 4 ret 3f 8 mov a,x 40 4 di 70 4 mov x,a 41 4 ei 72 4 mov psp,a 60 4 reti 73 8 call addr 50 - 5f 10 jc addr c0-cf 5 jmp addr 80-8f 5 jnc addr d0-df 5 call addr 90-9f 10 jacc addr e0-ef 7 jz addr a0-af 5 index addr f0-ff 14 jnz addr b0-bf 5
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 14 of 58 5.0 programming model 5.1 14-bit program counter (pc) the 14-bit program counter (pc) allows access to up to 8 kb of prom available with the cy7c66x13 architecture. the top 32 bytes of the rom in the 8k part are reserved for testing purposes. the program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. typically, this is a jump instruction to a reset handler that i nitializes the application (see section 16.1, interrupt vectors, on page 30). the lower eight bits of the program counter are incremented as instructions are loaded and executed. the upper six bits of the program counter are incremented by executing an xpage instruction. as a result, the last instruction executed within a 256-byte ?page? of sequential code should be an xpage instruction. the assembler directive ?xpageon? causes the assembler to insert xpage instructions automatically. because instructions can be either one or two bytes long, the assembler may occasionally need to insert a nop followed by an xpage to execute correctly. the address of the next instruction to be executed, the carry flag, and the zero flag are saved as two bytes on the program sta ck during an interrupt acknowledge or a call instruction. the program counter, carry flag, and zero flag are restored from the program stack during a reti instruction. only the program counter is restored during a ret instruction. the program counter cannot be accessed directly by the firmware. the program stack can be examined by reading sram from location 0x00 and up.
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 15 of 58 5.1.1 program memory organization after reset address 14-bit pc 0x0000 program execution begins here after a reset 0x0002 usb bus reset interrupt vector 0x0004 128- s timer interrupt vector 0x0006 1.024-ms timer interrupt vector 0x0008 usb address a endpoint 0 interrupt vector 0x000a usb address a endpoint 1 interrupt vector 0x000c usb address a endpoint 2 interrupt vector 0x000e usb address b endpoint 0 interrupt vector 0x0010 usb address b endpoint 1 interrupt vector 0x0012 hub interrupt vector 0x0014 dac interrupt vector 0x0016 gpio interrupt vector 0x0018 i 2 c interrupt vector 0x001a program memory begins here 0x1fdf 8 kb (-32) prom ends here (cy7c66013, cy7c66113) figure 5-1. program memory space with interrupt vector table
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 16 of 58 5.2 8-bit accumulator (a) the accumulator is the general-purpose register for the microcontroller. 5.3 8-bit temporary register (x) the ?x? register is available to the firmware for temporary stor age of intermediate results. the microcontroller can perform in dexed operations based on the value in x. refer to section 5.6.3 for additional information. 5.4 8-bit program stack pointer (psp) during a reset, the program stack pointer (psp) is set to 0x00 and ?grows? upward from this address. the psp may be set by firmware, using the mov psp,a instruction. the psp supports interrupt service under hardware control and call, ret, and reti instructions under firmware control. the psp is not readable by the firmware. during an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. the first byte is stored in the memory addressed by the psp, then the psp is incremented. the second byte is stored in memory addressed by the psp, and the psp is incremented again. the overall effect is to store the program counter and flags on the program ?stack? and increment the psp by two. the return from interrupt (reti) instruction decrements the psp, then restores the second byte from memory addressed by the psp. the psp is decremented again and the first byte is restored from memory addressed by the psp. after the program counter and flags have been restored from stack, the interrupts are enabled. the overall effect is to restore the program counter and f lags from the program stack, decrement the psp by two, and reenable interrupts. the call subroutine (call) instruction stores the program counter and flags on the program stack and increments the psp by two. the return from subroutine (ret) instruction restores the program counter but not the flags from the program stack and decrements the psp by two. 5.4.1 data memory organization the cy7c66x13 microcontrollers provide 256 bytes of data ram. normally, the sram is partitioned into four areas: program stack, user variables, data stack, and usb endpoint fifos. the following is one example of where the program stack, data stack, and user variables areas could be located. 5.5 8-bit data stack pointer (dsp) the data stack pointer (dsp) supports push and pop instructions that use the data stack for temporary storage. a push instruction pre-decrements the dsp, then writes data to the memory location addressed by the dsp. a pop instruction reads data from the memory location addressed by the dsp, then post-increments the dsp. during a reset, the dsp is reset to 0x00. a push instruction when dsp equals 0x00 writes data at the top of the data ram (address 0xff). this writes data to the memory area reserved for usb endpoint fifos. therefore, the dsp should be indexed at an appropriate memory location that does not compromise the program stack, user-defined memory (variables), or the usb endpoint fifos. notes: 1. refer to section 5.5 for a description of dsp. 2. endpoint sizes are fixed by the endpoint size bit (i/o register 0x1f, bit 7), see tab le 1 9-1 . after reset address 8-bit dsp 8-bit psp 0x00 program stack growth (move dsp [1] ) 8-bit dsp user selected data stack growth user variables usb fifo space for up to two addresses and five endpoints [2] 0xff
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 17 of 58 for usb applications, the firmware should set the dsp to an appropriate location to avoid a memory conflict with ram dedicated to usb fifos. the memory requirements for the usb endpoints are described in section 19.2. example assembly instructions to do this with two device addresses (fifos begin at 0xd8) are shown below: mov a,20h ; move 20 hex into accumulator (must be d8h or less) swap a,dsp ; swap accumulator value into dsp register. 5.6 address modes the cy7c66013 and cy7c66113 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 5.6.1 data (immediate) ?data? address mode refers to a data operand that is actually a constant encoded in the instruction. as an example, consider th e instruction that loads a with the constant 0xd8: mov a, 0d8h. this instruction requires two bytes of code where the first byte identifies the ?mov a? instruction with a data operand as the second byte. the second byte of the instruction is the constant ?0xd8?. a constant may be referred to by name if a prior ?equ? statement assigns the constant value to the name. for example, the following code is equivalent to the example shown above: dspinit: equ 0d8h mov a, dspinit. 5.6.2 direct ?direct? address mode is used when the data operand is a variable stored in sram. in that case, the one byte address of the variable is encoded in the instruction. as an example, consider an instruction that loads a with the contents of memory address location 0x10: mov a, [10h]. normally, variable names are assigned to variable addresses using ?equ? statements to improve the readability of the assembler source code. as an example, the following code is equivalent to the example shown above: buttons: equ 10h mov a, [buttons]. 5.6.3 indexed ?indexed? address mode allows the firmware to manipulate arrays of data stored in sram. the address of the data operand is the sum of a constant encoded in the instruction and the contents of the ?x? register. normally, the constant is the ?base? add ress of an array of data and the x register contains an index that indicates which element of the array is actually addressed: array: equ 10h mov x, 3 mov a, [x+array]. this would have the effect of loading a with the fourth element of the sram ?array? that begins at address 0x10. the fourth element would be at address 0x13. 6.0 clocking the xtalin and xtalout are the clock pins to the microcontroller. the user can connect an external oscillator or a crystal to these pins. when using an external crystal, keep pcb traces between the chip leads and crystal as short as possible (less than 2 cm). a 6-mhz fundamental frequency parallel resonant crystal can be connected to these pins to provide a reference frequency for the internal pll. the two internal 30-pf load caps appear in series to the external crystal and would be equivalent to a 15 -pf xtalout xtalin to internal pll 30 pf 30 pf (pin 1) (pin 2) figure 6-1. clock oscillator on-chip circuit
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 18 of 58 load. therefore, the crystal must have a required load capacitance of about 15?18 pf. a ceramic resonator does not allow the microcontroller to meet the timing specifications of full speed usb and therefore a ceramic resonator is not recommended with these parts. an external 6-mhz clock can be applied to the xtalin pin if the xtalout pin is left open. grounding the xtalout pin when driving xtalin with an oscillator does not work because the internal clock is effectively shorted to ground. 7.0 reset the cy7c66x13 supports two resets: por and a watchdog reset (wdr). each of these resets causes: all registers to be restored to their default states the usb device addresses to be set to 0 all interrupts to be disabled the psp and dsp to be set to memory address 0x00. the occurrence of a reset is recorded in the processor status and control register, as described in section 15.0. bits 4 and 6 are used to record the occurrence of por and wdr, respectively. firmware can interrogate these bits to determine the cause of a reset. program execution starts at rom address 0x0000 after a reset. although this looks like interrupt vector 0, there is an importan t difference. reset processing does not push the program counter, carry flag, and zero flag onto program stack. the firmware reset handler should configure the hardware before the ?main? loop of code. attempting to execute a ret or reti in the firmware reset handler causes unpredictable execution results. 7.1 power-on reset when v cc is first applied to the chip, the por signal is asserted and the cy7c66x13 enters a ?semi-suspend? state. during the semi-suspend state, which is different from the suspend state defined in the usb specification, the oscillator and all other bl ocks of the part are functional, except for the cpu. this semi-suspend time ensures that both a valid v cc level is reached and that the internal pll has time to stabilize before full operation begins. when the v cc has risen above approximately 2.5v, and the oscillator is stable, the por is deasserted and the on-chip timer starts counting. the first 1 ms of suspend time is not interr uptible, and the semi-suspend state continues for an additional 95 ms unless the count is bypassed by a usb bus reset on the upstream port. the 95 ms provides time for v cc to stabilize at a valid operating voltage before the chip executes code. if a usb bus reset occurs on the upstream port during the 95 ms semi-suspend time, the semi-suspend state is aborted and program execution begins immediately from address 0x0000. in this case, the bus reset interrupt is pending but not serviced until firmware sets the usb bus reset interrupt enable bit (bit 0 of register 0x20) and enables interrupts with the ei command. the por signal is asserted whenever v cc drops below approximately 2.5v, and remains asserted until v cc rises above this level again. behavior is the same as described above. 7.2 watchdog reset the wdr occurs when the internal wdt rolls over. writing any value to the write-only watchdog restart register at address 0x26 clears the timer. the timer rolls over and wdr occurs if it is not cleared within t watch (8 ms minimum) of the last clear. bit 6 of the processor status and control register is set to record this event (the register contents are set to 010x0001 by the wd r). a wdt reset lasts for 2 ms, after which the microcontroller begins execution at rom address 0x0000. the usb transmitter is disabled by a wdr because the usb device address registers are cleared (see section 19.1). otherwise, the usb controller would respond to all address 0 transactions. last write to wdt register no write to wdt register, so wdr goes high execution begins at reset vector 0x0000 t watch 2 ms figure 7-1. watchdog reset
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 19 of 58 it is possible for the wdr bit of the processor status and control register (0xff) to be set following a por event. if a firmwa re interrogates the processor status and control register for a set condition on the wdr bit, the wdr bit should be ignored if the por (bit 3 of register 0xff) bit is set. 8.0 suspend mode the cy7c66x13 can be placed into a low-power state by setting the suspend bit of the processor status and control register. all logic blocks in the device are turned off except the gpio interrupt logic and the usb receiver. the clock oscillator and pl l, as well as the free-running and wdts, are shut down. only the occurrence of an enabled gpio interrupt or non-idle bus activity at a usb upstream or downstream port wakes the part from suspend. the run bit in the processor status and control register must be set to resume a part out of suspend. the clock oscillator restarts immediately after exiting suspend mode. the microcontroller returns to a fully functional state 1 ms after the oscillator is stable. the microcontroller executes the instruction following the i/o write that placed the device int o suspend mode before servicing any interrupt requests. the gpio interrupt allows the controller to wake-up periodically and poll system components while maintaining a very low averag e power consumption. to achieve the lowest possible current during suspend mode, all i/o should be held at v cc or gnd. this also applies to internal port pins that may not be bonded in a particular package. typical code for entering suspend is shown below: ... ; all gpio set to low-power state (no floating pins) ... ; enable gpio interrupts if desired for wake-up mov a, 09h ; set suspend and run bits iowr ffh ; write to status and control register ? enter suspend, wait for usb activity (or gpio interrupt) nop ; this executes before any isr ... ; remaining code for exiting suspend routine. 9.0 general-purpose i/o (gpio) ports figure 9-1. block diagram of a gpio pin gpio v cc 14 k ? gpio cfg mode 2-bits data out latch internal data bus port read port write interrupt enable control control interrupt controller q1 q3* q2 *port 0,1,2: low i sink port 3: high i sink data interrupt latch oe reg_bit strb data in latch (latch is transparent except in hapi mode) pin
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 20 of 58 there are up to 31 gpio pins (p0[7:0], p1[7:0], p2[7:0], and p3[6:0]) for the hardware interface. the number of gpio pins changes based on the package type of the chip. each port can be configured as inputs with internal pull-ups, open drain outputs , or traditional cmos outputs. port 3 offers a higher current drive, with typical current sink capability of 12 ma. the data for each gpio port is accessible through the data registers. port data registers are shown in figure 9-2 through figure 9-5 , and are set to 1 on reset. port 0 data address 0x00 port 1 data address 0x01 port 2 data address 0x02 port 3 data address 0x03 special care should be taken with any unused gpio data bits. an unused gpio data bit, either a pin on the chip or a port bit th at is not bonded on a particular package, must not be left floating when the device enters the suspend state. if a gpio data bit i s left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the usb specifications. if a ?1? is written to the unused data bit and the port is configured with open drain outputs, the unused data bit remains in an indeterminate state. therefore, if an unused port bit is programmed in open-drain mode, it must be written with a ?0.? notice that the cy7c66013 always requires that p3[7:5] be written with a ?0.? when the cy7c66113 is used the p3[7] should be written with a ?0.? in normal non-hapi mode, reads from a gpio port always return the present state of the voltage at the pin, independent of the settings in the port data registers. if hapi mode is activated for a port, reads of that port return latched data as controlled by the hapi signals (see section 14.0). during reset, all of the gpio pins are set to a high impedance input state (?1? in open drain mode). writing a ?0? to a gpio pin drives the pin low. in this state, a ?0? is always read on that gpio pin unless an external source overdrives the internal pull-down device. 9.1 gpio configuration port every gpio port can be programmed as inputs with internal pull-ups, outputs low or high, or hi-z (floating, the pin is not driv en internally). in addition, the interrupt polarity for each port can be programmed. the port configuration bits ( figure 9-6 ) and the interrupt enable bit ( figure 9-7 through figure 9-10 ) determine the interrupt polarity of the port pins. gpio configuration address 0x08 bit #76543210 bit name p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset11111111 figure 9-2. port 0 data bit #76543210 bit name p1.7 p1.6 p1.5 p1.4 reserved p1.2 p1.1 p1.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset11111111 figure 9-3. port1 data bit #76543210 bit name p2.7 p2.6 p2.5 p2.4 p2.3 reserved reserved reserved read/write r/w r/w r/w r/w r/w r/w r/w r/w reset11111111 figure 9-4. port 2 data bit #76543210 bit name reserved reserved reserved reserved reserved reserved p3.1 p3.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset11111111 figure 9-5. port 3 data bit #76543210 bit name port 3 config bit 1 port 3 config bit 0 port 2 config bit 1 port 2 config bit 0 port 1 config bit 1 port 1 config bit 0 port 0 config bit 1 port 0 config bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 figure 9-6. gpio configuration register
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 21 of 58 as shown in table 9-1 below, a positive polarity on an input pin represents a rising edge interrupt (low to high), and a negative polarity on an input pin represents a falling edge interrupt (high to low). the gpio interrupt is generated when all of the following conditions are met: the interrupt enable bit of the associated port interrupt enable register is enabled, the gpio interrupt enable bit of the global interrupt enable register ( figure 16-1 ) is enabled, the interrupt enable sense (bit 2, figure 15-1 ) is set, and the gpio pin of the port sees an event matching the interrupt polarity. the driving state of each gpio pin is determined by the value written to the pin?s data register ( figure 9-2 through figure 9-5 ) and by its associated port configuration bits as shown in the gpio configuration register ( figure 9-6 ). these ports are configured on a per-port basis, so all pins in a given port are configured together. the possible port configurations are detai led in table 9-1 . as shown in this table below, when a gpio port is configured with cmos outputs, interrupts from that port are disabled. during reset, all of the bits in the gpio configuration register are written with ?0? to select hi-z mode for all gpio ports as the default configuration. q1, q2, and q3 discussed below are the transistors referenced in figure 9-1 . the available gpio drive strength are: output low mode : the pin?s data register is set to ?0? writing ?0? to the pin?s data register puts the pin in output low mode, regardless of the contents of the port configuration bits[1:0]. in this mode, q1 and q2 are off. q3 is on. the gpio pin is driven low through q3. output high mode : the pin?s data register is set to 1 and the port configuration bits[1:0] is set to ?10? in this mode, q1 and q3 are off. q2 is on. the gpio is pulled up through q2. the gpio pin is capable of sourcing ... of current. resistive mode : the pin?s data register is set to 1 and the port configuration bits[1:0] is set to ?11? q2 and q3 are off. q1 is on. the gpio pin is pulled up with an internal 14k ? resistor. in resistive mode, the pin may serve as an input. reading the pin?s data register returns a logic high if the pin is not driven low by an external source. hi-z mode : the pin?s data register is set to1 and port configuration bits[1:0] is set either ?00? or ?01? q1, q2, and q3 are all off. the gpio pin is not driven internally. in this mode, the pin may serve as an input. reading the port data register returns the actual logic value on the port pins. 9.2 gpio interrupt enable ports each gpio pin can be individually enabled or disabled as an interrupt source. the port 0?3 interrupt enable registers provide this feature with an interrupt enable bit for each gpio pin. when hapi mode (section 14.0) is enabled the gpio interrupts are blocked, including ports not used by hapi, so gpio pins cannot be used as interrupt sources. during a reset, gpio interrupts are disabled by clearing all of the gpio interrupt enable ports. writing a ?1? to a gpio interr upt enable bit enables gpio interrupts from the corresponding input pin. all gpio pins share a common interrupt, as discussed in section 16.8. port 0 interrupt enable address 0x04 table 9-1. gpio port output control truth table and interrupt polarity port config bit 1 port config bit 0 data register output drive strength interrupt enable bit interrupt polarity 1 1 0 output low 0 disabled 1 resistive 1 ? (falling edge) 1 0 0 output low 0 disabled 1 output high 1 disabled 0 1 0 output low 0 disabled 1 hi-z 1 ? (falling edge) 0 0 0 output low 0 disabled 1 hi-z 1 + (rising edge) bit #76543210 bit name p0.7 intr enable p0.6 intr enable p0.5 intr enable p0.4 intr enable p0.3 intr enable p0.2 intr enable p0.1 intr enable p0.0 intr enable read/writewwwwwwww reset00000000 figure 9-7. port 0 interrupt enable
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 22 of 58 port 1 interrupt enable address 0x05 port 2 interrupt enable address 0x06 port 3 interrupt enable address 0x07 10.0 dac port the cy7c66113 features a programmable sink current 8 bit port which is also known as dac port. each of these port i/o pins have a programmable current sink. writing a ?1? to a dac i/o pin disables the output current sink (i sink dac) and drives the i/o pin high through an integrated 14-k ? resistor. when a ?0? is written to a dac i/o pin, the i sink dac is enabled and the pull-up resistor is disabled. this causes the i sink dac to sink current to drive the output low. figure 10-1 shows a block diagram of the dac port pin. the amount of sink current for the dac i/o pin is programmable over 16 values based on the contents of the dac isink register ( figure 10-3 ) for that output pin. dac[1:0] are high current outputs that are programmable from 3.2 ma to 16 ma (typical). dac[7:2] are low current outputs, programmable from 0.2 ma to 1.0 ma (typical). when the suspend bit in processor status and control register ( figure 15-1 ) is set, the isink dac block of the dac circuitry is disabled. special care should be taken when the cy7c66113 device is placed in the suspend. the dac port data register( figure 10-2 ) should normally be loaded with all ?1?s ( figure 15-1 ) before setting the suspend bit. if any of the dac bits bit #76543210 bit name p1.7 intr enable p1.6 intr enable p1.5 intr enable p1.4 intr enable reserved p0.2 intr enable p1.1 intr enable p1.0 intr enable read/writewwwwwwww reset00000000 figure 9-8. port 1 interrupt enable bit #76543210 bit name p0.7 intr enable p0.6 intr enable p0.5 intr enable p0.4 intr enable p0.3 intr enable reserved reserved reserved read/writewwwwwwww reset00000000 figure 9-9. port 2 interrupt enable bit #76543210 bit name reserved reserved reserved reserved reserved reserved p3.1 intr enable p0.3 intr enable read/writewwwwwwww reset00000000 figure 9-10. port 3 interrupt enable figure 10-1. block diagram of a dac pin v cc 14 k ? data out latch internal data bus dac read dac write interrupt enable interrupt logic to interrupt controller q1 internal buffer interrupt polarity isink dac isink register 4 bits dac i/o pin suspend (bit 3 of register 0xff)
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 23 of 58 are set to ?0? when the device is suspended, that dac input will float. the floating pin could result in excessive current cons umption by the device, unless an external load places the pin in a deterministic state. dac port data address 0x30 bit [1..0]: high current output 3.2 ma to 16 ma typical 1= i/o pin is an output pulled hgh through the 14-k ? resistor. 0 = i/o pin is an input with an internal 14-k ? pull-up resistor. bit [7..2]: low current output 0.2 ma to 1 ma typical 1= i/o pin is an output pulled hgh through the 14-k ? resistor. 0 = i/o pin is an input with an internal 14-k ? pull-up resistor. 10.1 dac isink registers each dac i/o pin has an associated dac isink register to program the output sink current when the output is driven low. the first isink register (0x38) controls the current for dac[0], the second (0x39) for dac[1], and so on until the isink register a t 0x3f, controls the current to dac[7]. dac sink register address 0x38 ?0x3f bit [4..0]: isink [x] (x= 0..4) writing all ?0?s to the isink register causes 1/5 of the max current to flow through the dac i/o pin. writing all ?1?s to the isink register provides the maximum current flow through the pin. the other 14 states of the dac sink current are evenly spaced between these two values. bit [7..5]: reserved 10.2 dac port interrupts a dac port interrupt can be enabled/disabled for each pin individually. the dac port interrupt enable register provides this feature with an interrupt enable bit for each dac i/o pin. all of the dac port interrupt enable register bits are cleared to ?0 ? during a reset. all dac pins share a common interrupt, as explained in section 16.7. dac port interrupt address 0x31 bit [7..0]: enable bit x (x= 0..7) 1= enables interrupts from the corresponding bit position; 0= disables interrupts from the corresponding bit position as an additional benefit, the interrupt polarity for each dac pin is programmable with the dac port interrupt polarity register . writing a ?0? to a bit selects negative polarity (falling edge) that causes an interrupt (if enabled) if a falling edge transit ion occurs on the corresponding input pin. writing a ?1? to a bit in this register selects positive polarity (rising edge) that causes an interrupt (if enabled) if a rising edge transition occurs on the corresponding input pin. all of the dac port interrupt polarity register bits are cleared during a reset. dac port interrupt address 0x32 bit #76543210 bit name dac[7] dac[6] dac[5] dac[4] dac[3] dac[2] dac[1] dac[0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset11111111 figure 10-2. dac port data bit #76543210 bit name reserved reserved reserved reserved isink[3] isink[2] isink[1] isink[0] read/write wwww reset----0000 figure 10-3. dac sink register bit #76543210 bit name enable bit 7 enable bit 6 enable bit 5 enable bi t 4 enable bit 3 enable bit 2 enable bit 1 enable bit 0 read/writewwwwwwww reset00000000 figure 10-4. dac port interrupt enable bit #76543210 bit name enable bit 7 enable bit 6 enable bit 5 enable bi t 4 enable bit 3 enable bit 2 enable bit 1 enable bit 0 read/writewwwwwwww figure 10-5. dac port interrupt polarity
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 24 of 58 bit [7..0]: enable bit x (x= 0..7) 1= selects positive polarity (rising edge) that causes an interrupt (if enabled); 0= selects negative polarity (falling edge) that causes an interrupt (if enabled). 11.0 12-bit free-running timer the 12-bit timer operates with a 1- s tick, provides two interrupts (128 s and 1.024 ms) and allows the firmware to directly time events that are up to 4 ms in duration. the lower eight bits of the timer can be read directly by the firmware. reading the low er 8 bits latches the upper four bits into a temporary register. when the firmware reads the upper four bits of the timer, it is a ctually reading the count stored in the temporary register. the effect of this is to ensure a stable 12-bit timer value can be read, ev en when the two reads are separated in time. timer lsb address 0x24 bit [7:0]: timer lower eight bits timer msb address 0x25 bit [3:0]: timer higher nibble bit [7:4]: reserved 12.0 i 2 c and hapi configuration register internal hardware supports communication with external devices through two interfaces: a two-wire i 2 c-compatible, and a hapi for 1, 2, or 3 byte transfers. the i 2 c-compatible and hapi functions, discussed in detail in sections 13.0 and 14.0, share a common configuration register (see figure 12-1 ) [3] . all bits of this register are cleared on reset. i 2 c configuration address 0x09 reset00000000 bit #76543210 bit name timer bit 7 timer bit 6 timer bit 5 timer bit 4 timer bit 3 timer bit 2 timer bit 1 timer bit 0 read/writerrrrrrrr reset00000000 figure 11-1. timer lsb register bit #76543210 bit name reserved reserved reserved reserved timer bit 11 timer bit 10 timer bit 9 timer bit 8 read/write----rrrr reset00000000 figure 11-2. timer msb register bit #76543210 bit name i 2 c position reserved lempty polarity drdy polarity latch empty data ready hapi port width bit 1 hapi port width bit 0 read/write r/w - r/w r/w r r r/w r/w figure 12-1. hapi/i 2 c configuration register figure 10-5. dac port interrupt polarity 10 9 7 85 6432 1 mhz clock 1.024-ms interrupt 128- s interrupt to timer registers 8 1 0 11 l1 l0 l2 l d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 11-3. timer block diagram
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 25 of 58 note: 3. i 2 c-compatible function must be separately enabled, as described in section 13.0. bits [7,1:0] of the hapi/i 2 c configuration register control the pin out configuration of the hapi and i 2 c-compatible interfaces. bits [5:2] are used in hapi mode only, and are described in section 14.0. table 12-1 shows the hapi port configurations, and table 12-2 shows i 2 c pin location configuration options. these i 2 c-compatible options exist due to pin limitations in certain packages, and to allow simultaneous hapi and i 2 c-compatible operation. hapi operation is enabled whenever either hapi port width bit (b it 1 or 0) is non-zero. this affects gpio operation as describe d in section 14.0. the i 2 c-compatible interface must be separately enabled as described in section13.0. 13.0 i 2 c-compatible controller the i 2 c-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and multi-master modes of operation. the i 2 c-compatible block functions by handling the low-level signaling in hardware, and issuing interrupts as needed to allow firmware to take appropriate action during transactions. while waiting for firmware response, the hardware keeps the i 2 c-compatible bus idle if necessary. the i 2 c-compatible interface generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a stop bit is detected by the slave when in receive mode, or when arbitration is lost. details of the interrupt responses are g iven in section 16.9. the i 2 c-compatible interface consists of two registers, an i 2 c data register ( figure 13-1 ) and an i 2 c status and control register ( figure 13-2 ). the data register is implemented as separate read and write registers. generally, the i 2 c status and control register should only be monitored after the i 2 c interrupt, as all bits are valid at that time. polling this register at other times could read misleading bit status if a transaction is underway. the i 2 c scl clock is connected to bit 0 of gpio port 1 or gpio port 2, and the i 2 c sda data is connected to bit 1 of gpio port 1 or gpio port 2. refer to section 12.0 for the bit definitions and functionality of the hapi/i 2 c configuration register, which is used to set the locations of the configurable i 2 c pins. once the i 2 c-compatible functionality is enabled by setting bit 0 of the i 2 c status & control register, the two lsb ([1:0]) of the corresponding gpio port is placed in open drain mode, regardless of the settings of the gpio configuration register. the electrical characteristics of the i 2 c-compatible interface is the same as that of gpio ports 1 and 2. note that the i ol (max) is 2 ma @ v ol = 2.0v for ports 1 and 2. all control of the i 2 c clock and data lines is performed by the i 2 c-compatible block. i 2 c data address 0x29 bits [7..0] : i 2 c data contains 8-bit data on the i 2 c bus. i 2 c status and control address 0x28 reset00000000 table 12-1. hapi port configuration port width (bit 0 and 1, figure 12-1 ) hapi port width 11 24 bits: p3[7:0], p1[7:0], p0[7:0] 10 16 bits: p1[7:0], p0[7:0] 01 8 bits: p0[7:0] 00 no hapi interface table 12-2. i 2 c port configuration i 2 c position (bit 7, figure 12-1 )i 2 c port width (bit 1, figure 12-1 ) i 2 c position don?t care 1 i 2 c on p2[1:0], 0:scl, 1:sda 00i 2 c on p1[1:0], 0:scl, 1:sda 10i 2 c on p2[1:0], 0:scl, 1:sda bit #76543210 bit name i 2 c data 7 i 2 c data 6 i 2 c data 5 i 2 c data 4 i 2 c data 3 i 2 c data 2 i 2 c data 1 i 2 c data 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w resetxxxxxxxx figure 13-1. i 2 c data register bit #76543210 figure 13-2. i 2 c status and control register figure 12-1. hapi/i 2 c configuration register
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 26 of 58 the i 2 c status and control register bits are defined in table 14-1 , with a more detailed description following. bit 7 : mstr mode setting this bit to 1 causes the i 2 c-compatible block to initiate a master mode transaction by sending a start bit and transmitting the first data byte from the data register (this typically holds the target address and r/w bit). subsequent bytes are initiated by setting the continue bit, as described below. clearing this bit (set to 0) causes the gpio pins to operate normally in master mode, the i 2 c-compatible block generates the clock (sck), and drives the data line as required depending on transmit or receive state. the i 2 c-compatible block performs any required arbitration and clock synchronization. in the event of a loss of arbitration, this mstr bit is cleared, the arb lost bit is set, and an interrupt is generated by the microcontroller. if the chip is the target of an external master that wins arbitration, then the interrupt is held off until th e transaction from the external master is completed. when mstr mode is cleared from 1 to 0 by a firmware write, an i 2 c stop bit is generated. bit 6 : continue/busy this bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin. in other wor ds, the bit has responded to an interrupt request and has completed the required update or read of the data register. during a read this bit indicates if the hardware is busy and is locking out additional writes to the i 2 c status and control register. this locking allows the hardware to complete certain operations that may require an extended period of time. following an i 2 c interrupt, the i 2 c-compatible block does not return to the busy state until firmware sets the continue bit. this allows the firmware to make one control register write without the need to check the busy bit. bit 5 : xmit mode this bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. clearing this bit sets the part in receive mode. firmware generally determines the value of this bit from the r/w bit associated with the i 2 c address packet. the xmit mode bit state is ignored when initially writing the mstr mode or the restart bits, as these cases always cause transmit mode for the first byte. bit 4 : ack this bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ack signal on the i 2 c-compatible bus. writing a 1 to this bit generates an ack (sda low) on the i 2 c-compatible bus at the ack bit time. during transmits (xmit mode = 1), this bit should be cleared. bit 3 : addr bit name mstr mode continue/busy xmit mode ack addr arb lost/restart received stop i 2 c enable read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 table 13-1. i 2 c status and control register bit definitions bit name description 0 i 2 c enable when set to ?1?, the i 2 c-compatible function is enabled. when cleared, i 2 c gpio pins operate normally. 1 received stop reads 1 only in slave receive mode, when i 2 c stop bit detected (unless firmware did not ack the last transaction). 2 arb lost/restart reads 1 to indicate master has lost arbitration. reads 0 otherwise. write to 1 in master mode to perform a restart sequence (also set continue bit). 3 addr reads 1 during first byte after start/restart in slave mode, or if master loses arbitration. reads 0 otherwise. this bit should always be written as 0. 4 ack in receive mode, write 1 to generate ack, 0 for no ack. in transmit mode, reads 1 if ack was received, 0 if no ack received. 5 xmit mode write to 1 for transmit mode, 0 for receive mode. 6 continue/busy write 1 to indicate ready for next transaction. reads 1 when i 2 c-compatible block is busy with a transaction, 0 when transaction is complete. 7 mstr mode write to 1 for master mode, 0 for slave mode. this bit is cleared if master loses arbitration. clearing from 1 to 0 generates stop bit. figure 13-2. i 2 c status and control register
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 27 of 58 this bit is set by the i 2 c-compatible block during the first byte of a slave receive transaction, after an i 2 c start or restart. the addr bit is cleared when the firmware sets the continue bit. this bit allows the firmware to recognize when the master has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred. bit 2 : arb lost/restart this bit is valid as a status bit (arb lost) after master mode transactions. in master mode, set this bit (along with the continue and mstr mode bits) to perform an i 2 c restart sequence. the i 2 c target address for the restart must be written to the data register before setting the continue bit. to prevent false arb lost signals, the restart bit is cleared by hardware during the restart sequence. bit 1 : receive stop this bit is set when the slave is in receive mode and detects a stop bit on the bus. the receive stop bit is not set if the firmware terminates the i 2 c transaction by not acknowledging the previous byte transmitted on the i 2 c-compatible bus, e.g. in receive mode if firmware sets the continue bit and clears the ack bit. bit 0 : i 2 c enable set this bit to override gpio definition with i 2 c-compatible function on the two i 2 c-compatible pins. when this bit is cleared, these pins are free to function as gpios. in i 2 c-compatible mode, the two pins operate in open drain mode, independent of the gpio configuration setting. 14.0 hardware assisted parallel interface (hapi) the cy7c66x13 processor provides a hardware assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate data transfer with an external microcontroller or similar device. control bits for selecting the byte width are in the hapi/i 2 c configuration register ( figure 12-1 ), bits 1 and 0. signals are provided on port 2 to control the hapi interface. table 14-1 describes these signals and the hapi control bits in the hapi/i 2 c configuration register. enabling hapi causes the gpio setting in the gpio configuration register ( figure 9-6 ) to be overridden. the port 2 output pins are in cmos output mode and port 2 input pins are in input mode (open drain mode with q3 off in figure 9-1 ). hapi read by external device from cy7c66x13: in this case (see figure 25-3 ), firmware writes data to the gpio ports. if 16-bit or 24-bit transfers are being made, port 0 should be written last, since writes to port 0 asserts the data ready bit and the dreadypin to signal the external device that data is available. the external device then drives the oe and cs pins active (low), which causes the hapi data to be output on the port pins. when oe is returned high (inactive), the hapi/gpio interrupt is generated. at that point, firmware can reload the hapi latches for the next output, again writing port 0 last. the data ready bit reads the opposite state from the external dreadypin on pin p2[3]. if the drdy polarity bit is 0, dreadypin is active high, and the data ready bit is active low. hapi write by external device to cy7c66x13: table 14-1. port 2 pin and hapi configuration bit definitions pin name direction description (port 2 pin) p2[2] latemptypin out ready for more input data from external interface. p2[3] dreadypin out output data ready for external interface. p2[4] stb in strobe signal for latching incoming data. p2[5] oe in output enable, causes chip to output data. p2[6] cs in chip select (gates stb and oe ). bit name r/w description (hapi/i 2 c configuration register) 2 data ready r asserted after firmware writes data to port 0, until oe driven low. 3 latch empty r asserted after firmware reads data from port 0, until stb driven low. 4 drdy polarity r/w determines polarity of data ready bit and dreadypin: if 0, data ready is active low, dreadypin is active high. if 1, data ready is active high, dreadypin is active low. 5 lempty polarity r/w determines polarity of latch empty bit and latemptypin: if 0, latch empty is active low, latemptypin is active high. if 1, latch empty is active high, latemptypin is active low.
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 28 of 58 in this case (see figure 25-4 ), the external device drives the stb and cs pins active (low) when it drives new data onto the port pins. when this happens, the internal latches become full, which causes the latch empty bit to be deasserted. when stb is returned high (inactive), the hapi/gpio interrupt is generated. firmware then reads the parallel ports to empty the hapi latches. if 16-bit or 24-bit transfers are being made, port 0 should be read last because reads from port 0 assert the latch em pty bit and the latemptypin to signal the external device for more data. the latch empty bit reads the opposite state from the external latemptypin on pin p2[2]. if the lempty polarity bit is 0, latemptypin is active high, and the latch empty bit is active low. 15.0 processor status and control register processor status and control address 0xff bit 0: run this bit is manipulated by the halt instruction. when halt is executed, all the bits of the processor status and control register are cleared to 0. since the run bit is cleared, the processor stops at the end of the current instruction. the process or remains halted until an appropriate reset occurs (power-on or watchdog). this bit should normally be written as a ?1.? bit 1: reserved bit 1 is reserved and must be written as a zero. bit 2: interrupt enable sense this bit indicates whether interrupts are enabled or disabled. firmware has no direct control over this bit as writing a zero or one to this bit position has no effect on interrupts. a ?0? indicates that interrupts are masked off and a ?1? indicates tha t the interrupts are enabled. this bit is further gated with the bit settings of the global interrupt enable register ( figure 16-1 ) and usb end point interrupt enable register ( figure 16-2 ). instructions di, ei, and reti manipulate the state of this bit. bit 3: suspend writing a ?1? to the suspend bit halts the processor and cause the microcontroller to enter the suspend mode that signifi- cantly reduces power consumption. a pending, enabled interrupt or usb bus activity causes the device to come out of suspend. after coming out of suspend, the device resumes firmware execution at the instruction following the iowr which put the part into suspend. an iowr attempting to put the part into suspend is ignored if usb bus activity is present. see section 8.0 for more details on suspend mode operation. bit 4: power-on reset the power-on reset is set to ?1? during a power-on reset. the firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a power-on condition or a watchdog timeout. a por event may be followed by a wdr before firmware begins executing, as explained below. bit 5: usb bus reset interrupt the usb bus reset interrupt bit is set when the usb bus reset is detected on receiving a usb bus reset signal on the upstream port. the usb bus reset signal is a single-ended zero (se0) that lasts from 12 to 16 s. an se0 is defined as the condition in which both the d+ line and the d? line are low at the same time. bit 6: wdr the wdr is set during a reset initiated by the wdt. this indicates the wdt went for more than t watch (8 ms minimum) between watchdog clears. this can occur with a por event, as noted below. bit 7: irq pending the irq pending, when set, indicates that one or more of the interrupts has been recognized as active. an interrupt remains pending until its interrupt enable bit is set ( figure 16-1 , figure 16-2 ) and interrupts are globally enabled. at that point, the internal interrupt handling sequence clears this bit until another interrupt is detected as pending. during power-up, the processor status and control register is set to 00010001, which indicates a por (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). during the 96 ms suspend at start-up (explained in section 7.1), a wdr also occurs unless this suspend is aborted by an upstream se0 before 8 ms. if a wdr occurs during the power-up suspend interval, firmware reads 01010001 from the status and control register after power-up. normally, the por bit should be cleared so a subsequent wdr can be clearly identified. if an upstream bus reset is received before firmware examines this register, the bus reset bit m ay also be set. bit #76543210 bit name irq pending watchdog reset usb bus reset interrupt power-on reset suspend interrupt enable sense reserved run read/write r r/w r/w r/w r/w r r/w r/w reset00010001 figure 15-1. processor status and control register
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 29 of 58 during a wdr, the processor status and control register is set to 01xx0001, which indicates a wdr (bit 6 set) has occurred and no interrupts are pending (bit 7 clear). the wdr does not effect the state of the por and the bus reset interrupt bits. 16.0 interrupts interrupts are generated by the gpio/dac pins, the internal timers, i 2 c-compatible or hapi operation, the internal usb hub, or on various usb traffic conditions. all interrupts are maskable by the global interrupt enable register and the usb end point interrupt enable register. writing a ?1? to a bit position enables the interrupt associated with that bit position. global interrupt enable register address 0x20 bit 0 : usb bus rst interrupt enable 1= enable interrupt on a usb bus reset; 0 = disable interrupt on a usb bus reset (refer to section 14.3). bit 1 :128- s interrupt enable 1 = enable timer interrupt every 128 s; 0 = disable timer interrupt for every 128 s. bit 2 : 1.024-ms interrupt enable 1= enable timer interrupt every 1.024 ms ; 0 = disable timer interrupt every 1.024 ms. bit 3 : usb hub interrupt enable 1 = enable interrupt on a hub status change; 0 = disable interrupt due to hub status change. (refer to section 14.6.) bit 4 : reserved bit 5 : gpio interrupt enable 1 = enable interrupt on falling/rising edge on any gpio; 0 = disable interrupt on falling/rising edge on any gpio. (refer to subsections 14.7, 9.1, and 9.2.) bit 6 : i 2 c interrupt enable 1= enable interrupt on i2c related activity; 0 = disable i2c related activity interrupt. (refer to section 14.8.) bit 7 : reserved . usb endpoint interrupt enable address 0x21 bit 0: epa0 interrupt enable 1= enable interrupt on data activity through endpoint a0; 0= disable interrupt on data activity through endpoint a0. bit 1 : epa1 interrupt enable 1= enable interrupt on data activity through endpoint a1; 0= disable interrupt on data activity through endpoint a1. bit 2 : epa2 interrupt enable 1= enable interrupt on data activity through endpoint a2; 0= disable interrupt on data activity through endpoint a2. bit 3 : epb0 interrupt enable 1= enable interrupt on data activity through endpoint b0; 0= disable interrupt on data activity through endpoint b0. bit 4 : epb1 interrupt enable 1= enable interrupt on data activity through endpoint b1; 0= disable interrupt on data activity through endpoint b1. bit [7..5] : reserved bit #76543210 bit name reserved i 2 c interrupt enable gpio interrupt enable reserved usb hub interrupt enable 1.024-ms interrupt enable 128- s interrupt enable usb bus rst interrupt enable read/write - r/w r/w - r/w r/w r/w r/w reset- 00x0000 figure 16-1. global interrupt enable register bit #76543210 bit name reserved reserved reserved epb1 interrupt enable epb0 interrupt enable epa2 interrupt enable epa1 interrupt enable epa0 interrupt enable read/write---r/wr/wr/wr/wr/w reset---00000 figure 16-2. usb endpoint interrupt enable register
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 30 of 58 during a reset, the contents the global interrupt enable register and usb end point interrupt enable register are cleared, effectively, disabling all interrupts. the interrupt controller contains a separate flip-flop for each interrupt. see figure 16-3 for the logic block diagram of the interrupt controller. when an interrupt is generated, it is first registered as a pending interrupt. it stays pending until it is service d or a reset occurs. a pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enab le registers. the highest priority interrupt request is serviced following the completion of the currently executing instruction. when servicing an interrupt, the hardware does the following: 1. disables all interrupts by clearing the global interrupt enable bit in the cpu (the state of this bit can be read at bit 2 of the processor status and control register, figure 15-1 ). 2. clears the flip-flop of the current interrupt. 3. generates an automatic call instruction to the rom address associated with the interrupt being serviced (i.e., the interrupt vector, see section 16.1). the instruction in the interrupt table is typically a jmp instruction to the address of the interrupt service routine (isr). th e user can re-enable interrupts in the interrupt service routine by executing an ei instruction. interrupts can be nested to a level l imited only by the available stack space. the program counter value as well as the carry and zero flags (cf, zf) are stored onto the program stack by the automatic call instruction generated as part of the interrupt acknowledge process. the user firmware is responsible for ensuring that the processor state is preserved and restored during an interrupt. the push a instruction should typically be used as the first command in the isr to save the accumulator value and the pop a instruction should be used to restore the accumulator value just before the reti instruction. the program counter cf and zf are restored and interrupts are enabled when the reti instruction is executed. the di and ei instructions can be used to disable and enable interrupts, respectively. these instructions affect only the globa l interrupt enable bit of the cpu. if desired, ei can be used to re-enable interrupts while inside an isr, instead of waiting for the reti that exists the isr. while the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by examining the irq sense bit (bit 7 in the processor status and control register). 16.1 interrupt vectors the interrupt vectors supported by the usb controller are listed in table 16-1 . the lowest-numbered interrupt (usb bus reset interrupt) has the highest priority, and the highest-numbered interrupt (i 2 c interrupt) has the lowest priority. clr global interrupt interrupt acknowledge irqout usb reset clear interrupt interrupt priority encoder enable [0] d q 1 enable bit clr usb reset irq 128- s clr 128- s irq 1-ms clr 1-ms irq addra ep0 irq addra ep0 clr i 2 c irq vector enable [6] clk clr d q clk 1 i 2 c clr i 2 c int usb reset int addra ep1 irq addra ep1 clr irq sense irq controlled by di, ei, and reti instructions dac irq dac clr to cpu cpu gpio irq gpio clr hub irq hub clr addra ep2 irq addra ep2 clr addrb ep0 irq addrb ep0 clr addrb ep1 irq addrb ep1 clr (reg 0x20) (reg 0x20) clr enable [2] d q 1 clk addra enp2 int (reg 0x21) int enabl e sense figure 16-3. interrupt controller function diagram
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 31 of 58 although reset is not an interrupt, the first instruction executed after a reset is at prom address 0x0000h?which corresponds to the first entry in the interrupt vector table. because the jmp instruction is two bytes long, the interrupt vectors occupy t wo bytes. 16.2 interrupt latency interrupt latency can be calculated from the following equation: interrupt latency = (number of clock cycles remaining in the current instruction) + (10 clock cycles for the call instruction) + (5 clock cycles for the jmp instruction). for example, if a five-clock cycle instruction such as jc is being executed when an interrupt occurs, the first instruction of the interrupt service routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is issued. for a 12-mhz internal clock (6-mhz crystal), 20 clock periods is 20/12 mhz = 1.667 s. 16.3 usb bus reset interrupt the usb controller recognizes a usb reset when a single ended zero (se0) condition persists on the upstream usb port for 12?16 s. se0 is defined as the condition in which both the d+ line and the d? line are low. a usb bus reset may be recognized for an se0 as short as 12 s, but is always recognized for an se0 longer than 16 s. when a usb bus reset is detected, bit 5 of the processor status and control register (figure 15-1 ) is set to record this event. in addition, the controller clears the following registers: sie section: usb device address registers (0x10, 0x40) hub section: hub ports connect status (0x48) hub ports enable (0x49) hub ports speed (0x4a) hub ports suspend (0x4d) hub ports resume status (0x4e) hub ports se0 status (0x4f) hub ports data (0x50) hub downstream force (0x51). a usb bus reset interrupt is generated at the end of the usb bus reset condition when the se0 state is deasserted. if the usb reset occurs during the start-up delay following a por, the delay is aborted as described in section 7.1. 16.4 timer interrupt there are two periodic timer interrupts: the 128- s interrupt and the 1.024-ms interrupt. the user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the s uspend request first. table 16-1. interrupt vector assignments interrupt vector number rom address function not applicable 0x0000 execution after reset begins here 1 0x0002 usb bus reset interrupt 2 0x0004 128- s timer interrupt 3 0x0006 1.024-ms timer interrupt 4 0x0008 usb address a endpoint 0 interrupt 5 0x000a usb address a endpoint 1 interrupt 6 0x000c usb address a endpoint 2 interrupt 7 0x000e usb address b endpoint 0 interrupt 8 0x0010 usb address b endpoint 1 interrupt 9 0x0012 usb hub interrupt 10 0x0014 dac interrupt 11 0x0016 gpio interrupt 12 0x0018 i 2 c interrupt
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 32 of 58 16.5 usb endpoint interrupts there are five usb endpoint interrupts, one per endpoint. a usb endpoint interrupt is generated after the usb host writes to a usb endpoint fifo or after the usb controller sends a packet to the usb host. the interrupt is generated on the last packet of the transaction (e.g. on the host?s ack during an in, or on the device ack during on out). if no ack is received during an in transaction, no interrupt is generated. 16.6 usb hub interrupt a usb hub interrupt is generated by the hardware after a connect/disconnect change, babble, or a resume event is detected by the usb repeater hardware. the babble and resume events are additionally gated by the corresponding bits of the hub port enable register ( figure 18-3 ). the connect/disconnect event on a port does not generate an interrupt if the sie does not drive the port (i.e., the port is being forced). 16.7 dac interrupt each dac i/o pin can generate an interrupt, if enabled. the interrupt polarity for each dac i/o pin is programmable. a positive polarity is a rising edge input while a negative polarity is a falling edge input. all of the dac pins share a single interrupt vector, which means the firmware needs to read the dac port to determine which pin or pins caused an interrupt. if one dac pin has triggered an interrupt, no other dac pins can cause a dac interrupt until that pin has returned to its inact ive (non-trigger) state or the corresponding interrupt enable bit is cleared. the usb controller does not assign interrupt priority to different dac pins and the dac interrupt enable register is not cleared during the interrupt acknowledge process. 16.8 gpio/hapi interrupt each of the gpio pins can generate an interrupt, if enabled. the interrupt polarity can be programmed for each gpio port as part of the gpio configuration. all of the gpio pins share a single interrupt vector, which means the firmware needs to read th e gpio ports with enabled interrupts to determine which pin or pins caused an interrupt. a block diagram of the gpio interrupt logic is shown in figure 16-4 . refer to sections 9.1 and 9.2 for more information about setting gpio interrupt polarity and enabling individual gpio interrupts. if one port pin has triggered an interrupt, no other port pins can cause a gpio interrupt until that port pin has returned to i ts inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. the usb controller does not assign interrupt pri ority to different port pins and the port interrupt enable registers are not cleared during the interrupt acknowledge process. when hapi is enabled, the hapi logic takes over the interrupt vector and blocks any interrupt from the gpio bits, including ports/bits not being used by hapi. operation of the hapi interrupt is independent of the gpio specific bit interrupt enables, a nd is enabled or disabled only by bit 5 of the global interrupt enable register (0x20) when hapi is enabled. the settings of the gpio bit interrupt enables on ports/bits not used by hapi still effect the cmos mode operation of those ports/bits. the effect of modifying the interrupt bits while the port config bits are set to ?10? is shown in table 9-1 . the events that generate hapi interrupts are described in section 14.0. port register or gate gpio interrupt flip flop clr gpio pin 1 = enable 0 = disable port interrupt enable register 1 = enable 0 = disable interrupt priority encoder irqout interrupt vector d q m u x 1 (1 input per gpio pin) global gpio interrupt enable (bit 5, register 0x20) ira configuration figure 16-4. gpio interrupt structure
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 33 of 58 16.9 i 2 c interrupt the i 2 c interrupt occurs after various events on the i 2 c-compatible bus to signal the need for firmware interaction. this generally involves reading the i 2 c status and control register ( figure 13-2 ) to determine the cause of the interrupt, loading/reading the i 2 c data register as appropriate, and finally writing the processor status and control register (figure 15-1 ) to initiate the subsequent transaction. the interrupt indicates that status bits are stable and it is safe to read and write the i 2 c registers. refer to section 13.0 for details on the i 2 c registers. when enabled, the i 2 c-compatible state machines generate interrupts on completion of the following conditions. the referenced bits are in the i 2 c status and control register. 1. in slave receive mode, after the slave receives a byte of data: the addr bit is set, if this is the first byte since a start or restart signal was sent by the external master. firmware must read or write the data register as necessary, then set the ack, xmit mode, and continue/busy bits appropriately for the next byte. 2. in slave receive mode, after a stop bit is detected: the received stop bit is set, if the stop bit follows a slave receive transaction where the ack bit was cleared to 0, no stop bit detection occurs. 3. in slave transmit mode, after the slave transmits a byte of data: the ack bit indicates if the master that requested the byte acknowledged the byte. if more bytes are to be sent, firmware writ es the next byte into the data register and then sets the xmit mode and continue/busy bits as required. 4. in master transmit mode, after the master sends a byte of data. firmware should load the data register if necessary, and set the xmit mode, mstr mode , and continue/busy bits appropriately. clearing the mstr mode bit issues a stop signal to the i 2 c-compatible bus and return to the idle state. 5. in master receive mode, after the master receives a byte of data: firmware should read the data and set the ack and continue/busy bits appropriately for the next byte. clearing the mstr mode bit at the same time causes the master state machine to issue a stop signal to the i 2 c-compatible bus and leave the i 2 c-compatible hardware in the idle state. 6. when the master loses arbitration: this condition clears the mstr mode bit and sets the arb lost/restart bit immediately and then waits for a stop signal on the i 2 c-compatible bus to generate the interrupt. the continue/busy bit is cleared by hardware prior to interrupt conditions 1 to 4. once the data register has been read or written, firmware should configure the other control bits and set the continue/busy bit for subsequent transactions. following an interrupt from master mode, firmware should perform only one write to the status and control register that sets the continue/busy bit, without checking the value of the continue/busy bit. the busy bit may otherwise be active and i 2 c register contents may be changed by the hardware during the transaction, until the i 2 c interrupt occurs. 17.0 usb overview the usb hardware includes a usb hub repeater with one upstream and four downstream ports. the usb hub repeater interfaces to the microcontroller through a full-speed serial interface engine. an external series resistor of r ext must be placed in series with all upstream and downstream usb outputs in order to meet the usb driver requirements of the usb specification. the cy7c66x13 microcontroller can provide the functionality of a compound device consisting of a usb hub and permanently attached functions. 17.1 usb serial interface engine the sie allows the cy7c66x13 microcontroller to communicate with the usb host through the usb repeater portion of the hub. the sie simplifies the interface between the microcontroller and usb by incorporating hardware that handles the following usb bus activity independently of the microcontroller: bit stuffing/unstuffing checksum generation/checking ack/nak/stall token type identification address checking. firmware is required to handle the following usb interface tasks: coordinate enumeration by responding to setup packets fill and empty the fifos suspend/resume coordination verify and select data toggle values. 17.2 usb enumeration the internal hub and any compound device function are enumerated under firmware control. the hub is enumerated first, followed by any integrated compound function. after the hub is enumerated, the usb host can read hub connection status to determine which (if any) of the downstream ports need to be enumerated. the following is a brief summary of the typical enumeration process of the cy7c66x13 by the usb host. for a detailed description of the enumeration process, refer to the usb specification .
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 34 of 58 in this description, ?firmware? refers to embedded firmware in the cy7c66x13 controller. 1. the host computer sends a setup packet followed by a data packet to usb address 0 requesting the device descriptor. 2. firmware decodes the request and retrieves its device descriptor from the program memory tables. 3. the host computer performs a control read sequence and firmware responds by sending the device descriptor over the usb bus, via the on-chip fifos. 4. after receiving the descriptor, the host sends a setup packet followed by a data packet to address 0 assigning a new usb address to the device. 5. firmware stores the new address in its usb device address register (for example, as address b) after the no-data control sequence completes. 6. the host sends a request for the device descriptor using the new usb address. 7. firmware decodes the request and retrieves the device descriptor from program memory tables. 8. the host performs a control read sequence and firmware responds by sending its device descriptor over the usb bus. 9. the host generates control reads from the device to request the configuration and report descriptors. 10.once the device receives a set configuration request, its functions may now be used. 11.following enumeration as a hub, firmware can optionally indicate to the host that a compound device exists (for example, the keyboard in a keyboard/hub device). 12.the host carries out the enumeration process with this additional function as though it were attached downstream from the hu b. 13.when the host assigns an address to this device, it is stored as the other usb address (for example, address a). 18.0 usb hub a usb hub is required to support: connectivity behavior: service connect/disconnect detection bus fault detection and recovery full-/low-speed device support. these features are mapped onto a hub repeater and a hub controller. the hub controller is supported by the processor integrated into the cy7c66013 and cy7c66113 microcontrollers. the hardware in the hub repeater detects whether a usb device is connected to a downstream port and the interface speed of the downstream device. the connection to a downstream port is through a differential signal pair (d+ and d?). each downstream port provided by the hub requires external r udn resistors from each signal line to ground, so that when a downstream port has no device connected, the hub reads a low (zero) on both d+ and d?. this condition is used to identify the ?no connect? state. the hub must have a resistor r uup connected between its upstream d+ line and v reg to indicate it is a full speed usb device. the hub generates an eop at eof1, in accordance with the usb 1.1 specification, section 11.2.2. 18.1 connecting/disconnecting a usb device a low-speed (1.5 mbps) usb device has a pull-up resistor on the d? pin. at connect time, the bias resistors set the signal leve ls on the d+ and d? lines. when a low-speed device is connected to a hub port, the hub sees a low on d+ and a high on d?. this causes the hub repeater to set a connect bit in the hub ports connect status register for the downstream port. then the hu b repeater generates a hub interrupt to notify the microcontroller that there has been a change in the hub downstream status. a full-speed (12 mbps) usb device has a pull-up resistor from the d+ pin, so the hub sees a high on d+ and a low on d?. in this case, the hub repeater sets a connect bit in the hub ports connect status register, clears a bit in the hub ports speed re gister (for full-speed), and generates a hub interrupt to notify the microcontroller of the change in hub status. the firmware sets th e speed of this port in the hub ports speed register (see figure 18-2 ) connects are recorded by the time a non-se0 state lasts for more than 2.5 s on a downstream port. when a usb device is disconnected from the hub, the downstream signal pair eventually floats to a single-ended zero state. the hub repeater recognizes a disconnect once the se0 state on a downstream port lasts from 2.0 to 2.5 s. on a disconnect, the corresponding bit in the hub ports connect status register is cleared, and the hub interrupt is generated. hub ports connect status address 0x48 bit #76543210 bit name reserved port 7 connect status port 6 connect status port 5 connect status port 4 connect status port 3 connect status port 2 connect status port 1 connect status read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 figure 18-1. hub ports connect status
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 35 of 58 bit [0..6] : port x connect status (where x = 1..7) when set to 1, port x is connected; when set to 0, port x is disconnected. bit 7 : reserved . set to 0. the hub ports connect status register is cleared to zero by reset or usb bus reset, then set to match the hardware configuratio n by the hub repeater hardware. the reserved bit [7] should always read as ?0? to indicate no connection. hub ports speed address 0x4a bit [0..6] : port x speed (where x = 1..7) set to 1 if the device plugged in to port x is low speed; set to 0 if the device plugged in to port x is full speed. bit 7 : reserved. set to 0. the hub ports speed register is cleared to zero by reset or bus reset. this must be set by the firmware on issuing a port reset . the reserved bit [7] should always read as ?0.? 18.2 enabling/disabling a usb device after a usb device connection has been detected, firmware must update status change bits in the hub status change data structure that is polled periodically by the usb host. the host responds by sending a packet that instructs the hub to reset an d enable the downstream port. firmware then sets the bit in the hub ports enable register, figure 18-3 , for the downstream port. the hub repeater hardware responds to an enable bit in the hub ports enable register by enabling the downstream port, so that usb traffic can flow to and from that port. if a port is marked enabled and is not suspended, it receives all usb traffic from the upstream port, and usb traffic from the downstream port is passed to the upstream port (unless babble is detected). low-speed ports do not receive full-speed traffic from the upstream port. when firmware writes to the hub ports enable register to enable a port, the port is not enabled until the end of any packet cur rently being transmitted. if there is no usb traffic, the port is enabled immediately. when a usb device disconnection has been detected, firmware must update status bits in the hub change status data structure that is polled periodically by the usb host. in suspend, a connect or disconnect event generates an interrupt (if the hub inter rupt is enabled) even if the port is disabled. hub ports enable register address 0x49 bit [0..6] : port x enable (where x = 1..7) set to 1 if port x is enabled; set to 0 if port x is disabled. bit 7 : reserved. set to 0. the hub ports enable register is cleared to zero by reset or bus reset to disable all downstream ports as the default condition . a port is also disabled by internal hub hardware (enable bit cleared) if babble is detected on that downstream port. babble is defined as: any non-idle downstream traffic on an enabled downstream port at eof2 any downstream port with upstream connectivity established at eof2 (i.e., no eop received by eof2). 18.3 hub downstream ports status and control data transfer on hub downstream ports is controlled according to the bit settings of the hub downstream ports control register ( figure 18-4 ). each downstream port is controlled by two bits, as defined in table 18-1 below. the hub downstream ports control bit #76543210 bit name reserved port 7 speed port 6 speed port 5 speed port 4 speed port 3 speed port 2 speed port 1 speed read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 figure 18-2. hub ports speed bit #76543210 bit name reserved port 7 enable port 6 enable port 5 enable port 4 enable port 3 enable port 2 enable port 1 enable read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 figure 18-3. hub ports enable register
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 36 of 58 register is cleared upon reset or bus reset, and the reset state is the state for normal usb traffic. any downstream port being forced must be marked as disabled ( figure 18-3 ) for proper operation of the hub repeater. firmware should use this register for driving bus reset and resume signaling to downstream ports. controlling the port pins thr ough this register uses standard usb edge rate control according to the speed of the port, set in the hub port speed register. the downstream usb ports are designed for connection of usb devices, but can also serve as output ports under firmware control. this allows unused usb ports to be used for functions such as driving leds or providing additional input signals. pull ing up these pins to voltages above v ref may cause current flow into the pin. this register is not reset by bus reset. these bits must be cleared before going into suspend. hub downstream ports control register address 0x4b an alternate means of forcing the downstream ports is through the hub ports force low register ( figure 18-5 ) and hub ports force high register ( figure 18-6 ). with these registers the pins of the downstream ports can be individually forced low, or left unforced. unlike the hub downstream ports control register, above, the force low register does not produce standard usb edge rate control on the forced pins. however, this register allows downstream port pins to be held low in suspend. this regist er can be used to drive se0 on all downstream ports when unconfigured, as required in the usb 1.1 specification. hub ports force low address 0x51 hub ports force low address 0x52 the data state of downstream ports can be read through the hub ports se0 status register ( figure 18-7 ) and the hub ports data register ( figure 18-8 ). the data read from the hub ports data register is the differential data only and is independent of the settings of the hub ports speed register ( figure 18-2 ). when the se0 condition is sensed on a downstream port, the corresponding bits of the hub ports data register hold the last differential data state before the se0. hub ports se0 status register and hub ports data register are cleared upon reset or bus reset. hub ports se0 status address 0x4f bit #76543210 bit name port 4 control bit 1 port 4 control bit 0 port 3 control bit 1 port 3 control bit 0 port 2 control bit 1 port 2 control bit 0 port 1 control bit 1 port 1 control bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 figure 18-4. hub downstream ports control register table 18-1. control bit definition for downstream ports control bits control action bit1 bit 0 0 0 not forcing (normal usb function) 0 1 force differential ?1? (d+ high, d? low) 1 0 force differential ?0? (d+ low, d? high) 1 1 force se0 state bit #76543210 bit name force low d+[4] force low d-[4] force low d+[3] force low d?[3] force low d+[2] force low d?[2] force low d+[1] force low d?[1] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 figure 18-5. hub ports force low register bit #765 43 21 0 bit name reserved reserved force low d+[7] force low d?[7] force low d+[6] force low d?[6] force low d+[5] force low d?[5] read/write - - r/w r/w r/w r/w r/w r/w reset--0 00 00 0 figure 18-6. hub ports force low register bit #76543210 bit name reserved port 7 se0 status port 6 se0 status port 5 se0 status port 4 se0 status port 3 se0 status port 2 se0 status port 1 se0 status read/writerrrrrrrr reset00000000 figure 18-7. hub ports se0 status register
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 37 of 58 bit [0..6] : port x se0 status (where x = 1..7) set to 1 if a se0 is output on the port x bus; set to 0 if a non-se0 is output on the port x bus. bit 7 : reserved. set to 0. hub ports data address 0x50 bit [0..6] : port x diff data (where x = 1..7) set to 1 if d+ > d? (forced differential 1, if signal is differential, i.e. not a se0 or se1). set to 0 if d? > d+ (forced diff erential 0, if signal is differential, i.e., not a se0 or se1); bit 7 : reserved. set to 0. 18.4 downstream port suspend and resume the hub ports suspend register ( figure 18-9 ) and hub ports resume status register ( figure 18-10 ) indicate the suspend and resume conditions on downstream ports. the suspend register must be set by firmware for any ports that are selectively suspended. also, this register is only valid for ports that are selectively suspended. if a port is marked as selectively suspended, normal usb traffic is not sent to that port. resume traffic is also prevented fro m going to that port, unless the resume comes from the selectively suspended port. if a resume condition is detected on the port, hardware reflects a resume back to the port, sets the resume bit in the hub ports resume register, and generates a hub interrupt. if a disconnect occurs on a port marked as selectively suspended, the suspend bit is cleared. the device remote wakeup bit (bit 7) of the hub ports suspend register controls whether or not the resume signal is propagated by the hub after a connect or a disconnect event. if the device remote wakeup bit is set, the hub will automatically propagate the resume signal after a connect or a disconnect event. if the device remote wakeup bit is cleared, the hub will not propagate the resume signal. the setting of the device remote wakeup flag has no impact on the propagation of the resume signal after a downstream remote wakeup event. the hub will automatically propagate the resume signal after a remote wakeup event, regardless of the state of the device remote wakeup bit. the state of this bit has no impact on the generation of the hub inter rupt. these registers are cleared on reset or bus reset. these registers are cleared on reset or usb bus reset. hub ports suspend address 0x4d bit [0..6] : port x selective suspend (where x = 1..7) set to 1 if port x is selectively suspended; set to 0 if port x do not suspend. bit 7 : device remote wakeup. when set to 1, enable hardware upstream resume signaling for connect/disconnect events during global resume. when set to 0, disable hardware upstream resume signaling for connect/disconnect events during global resume. hub ports resume address 0x4e bit #76543210 bit name reserved port 7 diff. data port 6 diff. data port 5 diff. da ta port 4 diff. data port 3 diff. data port 2 diff. data port 1 di ff. data read/writerrrrrrrr reset00000000 figure 18-8. hub ports data register bit #76543210 bit name device remote wakeup port 7 selective suspend port 6 selective suspend port 5 selective suspend port 4 selective suspend port 3 selective suspend port 2 selective suspend port 1 selective suspend read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 figure 18-9. hub ports suspend register bit #76543210 bit name reserved resume 7 resume 6 resume 5 resume 4 resume 3 resume 2 resume 1 read/write- rrrrrrr reset00000000 figure 18-10. hub ports resume status register
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 38 of 58 bit [0..6] : resume x (where x = 1..7) when set to 1 port x requesting to be resumed (set by hardware); default state is 0; bit 7 : reserved . set to 0. resume from a selectively suspended port, with the hub not in suspend, typically involves these actions: 1. hardware detects the resume, drives a k to the port, and generates the hub interrupt. the corresponding bit in the resume status register (0x4e) reads ?1? in this case. 2. firmware responds to hub interrupt, and reads register 0x4e to determine the source of the resume. 3. firmware begins driving k on the port for 10 ms or more through register 0x4b. 4. firmware clears the selective suspend bit for the port (0x4d), which clears the resume bit (0x4e). this ends the hardware-dri v- en resume, but the firmware-driven resume continues. to preven t traffic being fed by the hub repeater to the port during or just after the resume, firmware should disable this port. 5. firmware drives a timed se0 on the port for two low-speed bit times as appropriate. note: firmware must disable interrupts during this se0 so the se0 pulse isn?t inadvertently lengthened and appears as a bus reset to the downstream device. 6. firmware drives a j on the port for one low-speed bit time, then it idles the port. 7. firmware re-enables the port. resume when the hub is suspended typically involves these actions: 1. hardware detects the resume, drives a k on the upstream (which is then reflected to all downstream enabled ports), and generates the hub interrupt. 2. the part comes out of suspend and the clocks start. 3. once the clocks are stable, firmware execution resumes. an internal counter ensures that this takes at least 1 ms. firmware should check for resume from any selectively suspended ports. if found, the selective suspend bit for the port should be cleared; no other action is necessary. 4. the resume ends when the host stops sending k from upstream. firmware should check for changes to the enable and connect registers. if a port has become disabled but is still connected, an se0 has been detected on the port. the port should be treated as having been reset, and should be reported to the host as newly connected. firmware can choose to clear the device remote wake-up bit (if set) to implement firmware timed states for port changes. all allowed port changes wake the part. then, the part can use internal timing to determine whether to take action or return to suspend. if device remote wake-up is set, automatic hardware assertions take place on resume events. 18.5 usb upstream port status and control usb status and control is regulated by the usb status and control register, as shown in figure 18-11 . all bits in the register are cleared during reset. usb status and control address 0x1f bits[2..0] : control action set to control action as per table 18-2 .the three control bits allow the upstream port to be driven manually by firmware. for normal usb operation, all of these bits must be cleared. table 18-2 shows how the control bits affect the upstream port. bit #76543210 bit name endpoint size endpoint mode d+ upstream d? upstream bus activity control action bit 2 control action bit 1 control action bit 0 read/write r/w r/w r r r/w r/w r/w r/w reset00000000 figure 18-11. usb status and control register
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 39 of 58 bit 3 : bus activity this is a ?sticky? bit that indicates if any non-idle usb event has occurred on the upstream usb port. firmware should check and clear this bit periodically to detect any loss of bus activity. writing a ?0? to the bus activity bit clears it, whil e writing a ?1? preserves the current value. in other words, the firmware can clear the bus activity bit, but only the sie can set it. bits 4 and 5 : d? upstream and d+ upstream these bits give the state of each upstream port pin individually: 1 = high, 0 = low. bit 6 : endpoint mode this bit used to configure the number of usb endpoints. see section 19.2 for a detailed description. bit 7 : endpoint size this bit used to configure the number of usb endpoints. see section 19.2 for a detailed description. the hub generates an eop at eof1 in accordance with the usb 1.1 specification, section 11.2.2. 19.0 usb sie operation the cy7c66x13 sie supports operation as a single device or a compound device. this section describes the two device addresses, the configurable endpoints, and the endpoint function. 19.1 usb device addresses the usb controller provides two usb device address registers: a (addressed at 0x10)and b (addressed at 0x40). upon reset and under default conditions, device a has three endpoints and device b has two endpoints. the usb device address register contents are cleared during a reset, setting the usb device addresses to zero and disabling these addresses. figure 19-1 shows the format of the usb address registers. usb device address (device a, b) addresses 0x10(a) and 0x40(b) bits[6..0] :device address firmware writes this bits during the usb enumeration process to the non-zero address assigned by the usb host. bit 7: device address enable must be set by firmware before the sie can respond to usb traffic to the device address. 19.2 usb device endpoints the cy7c66x13 controller supports up to two addresses and five endpoints for communication with the host. the configuration of these endpoints, and associated fifos, is controlled by bits [7,6] of the usb status and control register (see figure 18-11 ). bit 7 controls the size of the endpoints and bit 6 controls the number of addresses. these configuration options are detailed i n table 19-1 . endpoint fifos are part of user ram (as shown in section 5.4.1). table 18-2. control bit definition for upstream port control bits control action 000 not forcing (sie controls driver) 001 force d+[0] high, d?[0] low 010 force d+[0] low, d?[0] high 011 force se0; d+[0] low, d?[0] low 100 force d+[0] low, d?[0] low 101 force d+[0] hiz, d?[0] low 110 force d+[0] low, d?[0] hiz 111 force d+[0] hiz, d?[0] hiz bit #76543210 bit name device address enable device address bit 6 device address bit 5 device address bit 4 device address bit 3 device address bit 2 device address bit 1 device address bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 figure 19-1. usb device address registers
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 40 of 58 when the sie writes data to a fifo, the internal data bus is driven by the sie; not the cpu. this causes a short delay in the cpu operation. the delay is three clock cycles per byte. for example, an 8-byte data write by the sie to the fifo generates a delay of 2 s (3 cycles/byte * 83.33 ns/cycle * 8 bytes). 19.3 usb control endpoint mode registers all usb devices are required to have a control endpoint 0 (epa0 and epb0) that is used to initialize and control each usb address. endpoint 0 provides access to the device configuration information and allows generic usb status and control accesses. endpoint 0 is bidirectional to both receive and transmit data. the other endpoints are unidirectional, but selectable by the us er as in or out endpoints. the endpoint mode registers are cleared during reset. when usb status and control register bits [6,7] are set to [0,0] or [1,0] , the endpoint zero epa0 and epb0 mode registers use the format shown in figure 19-2 . usb device endpoint zero mode (a0, b0) addresses 0x12(a0) and 0x42(b0) bits[3..0] : mode these sets the mode which control how the control endpoint responds to traffic. bit 4 : ack this bit is set whenever the sie engages in a transaction to the register?s endpoint that completes with an ack packet. bit 5: endpoint 0 out received 1 = token received is an out token. 0 = token received is not an out token. this bit is set by the sie to report the type of token received by the corresponding device address is an out token. the bit must be cleared by firmware as part of the usb processing. bit 6: endpoint 0 in received 1 = token received is an in token. 0 = token received is not an in token. this bit is set by the sie to report the type of token received by the corresponding device address is an in token. the bit must be cleared by firmware as part of the usb processing. bit 7: endpoint 0 setup received 1 = token received is a setup token. 0 = token received is not a setup token. this bit is set only by the sie to report the type of token received by the corresponding device address is a setup token. any write to this bit by the cpu will clear it (set it to 0). the bit is forced high from the start of the data packet phase of the setup transaction until the start of the ack packet returned by the sie. the cpu should not clear this bit during this interval, and subsequently, until the cpu first does an iord to this endpoint 0 mode register. the bit must be cleared by firmware as part of the usb processing. note: in 5-endpoint mode (usb status and control register bits [7,6] are set to [0,1] or [1,1]), register 0x42 serves as non-control endpoint 3, and has the format for non-control endpoints shown in figure 19-3 . table 19-1. memory allocation for endpoints usb status and control register (0x1f) bits [7, 6] [0,0] [1,0] [0,1] [1,1] two usb addresses: a (3 endpoints) & b (2 endpoints) two usb addresses: a (3 endpoints) &b (2 endpoints) one usb address: a (5 endpoints) one usb address: a (5 endpoints) label start address size label start address size label start address size label start address size epb1 0xd8 8 epb0 0xa8 8 epa4 0xd8 8 epa3 0xa8 8 epb0 0xe0 8 epb1 0xb0 8 epa3 0xe0 8 epa4 0xb0 8 epa2 0xe8 8 epa0 0xb8 8 epa2 0xe8 8 epa0 0xb8 8 epa1 0xf0 8 epa1 0xc0 32 epa1 0xf0 8 epa1 0xc0 32 epa0 0xf8 8 epa2 0xe0 32 epa0 0xf8 8 epa2 0xe0 32 bit #7 6543210 bit name endpoint 0 setup received endpoint 0 in received endpoint 0 out received ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset0 0000000 figure 19-2. usb device endpoint zero mode registers
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 41 of 58 bits[6:0] of the endpoint 0 mode register are locked from cpu writ e operations whenever the sie has updated one of these bits, which the sie does only at the end of the token phase of a transaction (setup... data... ack, out... data... ack, or in... data ... ack). the cpu can unlock these bits by doing a subsequent read of this register. only endpoint 0 mode registers are locked when updated. the locking mechanism does not apply to the mode registers of other endpoints. because of these hardware locking features, firmware must perform an iord after an iowr to an endpoint 0 register. this verifie s that the contents have changed as desired, and that the sie has not updated these values. while the setup bit is set, the cpu cannot write to the endpoint zero fifos. this prevents firmware from overwriting an incomin g setup transaction before firmware has a chance to read the setup data. refer to table 19-1 for the appropriate endpoint zero memory locations. the mode bits (bits [3:0]) control how the endpoint responds to usb bus traffic. the mode bit encoding is shown in table 18-1 . additional information on the mode bits can be found in table 20-2 and table 20-1 . note: the sie offers an ?ack out - status in? mode and not an ?ack out - nak in? mode. therefore, if following the status stage of a control write transfer a usb host were to immediately start the next transfer, the new setup packet could override the dat a payload of the data stage of the previous control write. 19.4 usb non-control endpoint mode registers the format of the non-control endpoint mode registers is shown in figure 19-3 . usb non-control device endpoint mode addresses 0x14, 0x16, 0x44 bits[3..0] : mode these sets the mode which control how the control endpoint responds to traffic. the mode bit encoding is shown in table 18-1 . bit 4 : ack this bit is set whenever the sie engages in a transaction to the register?s endpoint that completes with an ack packet. bits[6..5] : reserved must be written zero during register writes. bit 7 : stall if this stall is set, the sie stalls an out packet if the mode bits are set to ack-in, and the sie stalls an in packet if the mode bits are set to ack-out. for all other modes, the stall bit must be a low. 19.5 usb endpoint counter registers there are five endpoint counter registers, with identical formats for both control and non-control endpoints. these registers contain byte count information for usb transactions, as well as bits for data packet status. the format of these registers is s hown in figure 19-4 . usb endpoint counter addresses 0x11, 0x13, 0x15, 0x41, 0x43 bits[5..0] : byte count these counter bits indicate the number of data bytes in a transaction. for in transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint fifo. valid values are 0 to 32, inclusive. for out or setup transactions, the count is updated by hardware to the number of data bytes received, plus two for the crc bytes. valid values are 2 to 34, inclusive. bit #76543210 bit name stall reserved reserved ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 figure 19-3. usb non-control device endpoint mode registers bit #76543210 bit name data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 figure 19-4. usb endpoint counter registers
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 42 of 58 bit 6 : data valid this bit is set on receiving a proper crc when the endpoint fifo buffer is loaded with data during transactions. this bit is used out and setup tokens only. if the crc is not correct, the endpoint interrupt occurs, but data valid is cleared to a zero. bit 7 : data 0/1 toggle this bit selects the data packet?s toggle state: 0 for data0, 1 for data1. for in transactions, firmware must set this bit to the desired state. for out or setup transactions, the hardware sets this bit to the state of the received data toggle bit. whenever the count updates from a setup or out transaction on endpoint 0, the counter register locks and cannot be written by the cpu. reading the register unlocks it. this prevents firmware from overwriting a status update on incoming setup or out transactions before firmware has a chance to read the data. only endpoint 0 counter register is locked when updated. the lockin g mechanism does not apply to the count registers of other endpoints. 19.6 endpoint mode/count registers update and locking mechanism the contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in figure 19-5 . two time points, update and setup, are shown in the same figure. the following activities occur at each time point: setup: the setup bit of the endpoint 0 mode register is forced high at this time. this bit is forced high by the sie until the end of the data phase of a control write transfer. the setup bit can not be cleared by firmware during this time. the affected mode and counter registers of endpoint 0 are locked from any cpu writes once they are updated. these registers can be unlocked by a cpu read, only if the read operation occurs after the update. the firmware needs to perform a register read as a part of the endpoint isr processing to unlock the effected registers. the locking mechanism on mode and counter registers ensures that the firmware recognizes the changes that the sie might have made since the previous io read of that register. update: 1. endpoint mode register ? all the bits are updated (except the setup bit of the endpoint 0 mode register). 2. counter registers ? all bits are updated. 3. interrupt ? if an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpo int is set at this time. for details on what conditions are required to generate an endpoint interrupt, refer to table 20-2 . 4. the contents of the updated endpoint 0 mode and counter registers are locked, except the setup bit of the endpoint 0 mode register which was locked earlier.
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 43 of 58 a c k 1. in token h o s t d e v i c e s y n c in a d d r c r c 5 e n d p s y n c d a t a 1/0 c r c 16 s y n c data token packet data packet hand shake packet update host to device device to host host to device s y n c in a d d r c r c 5 e n d p token packet host to device s y n c data packet device to host nak/stall update 2. out or setup token without crc error s y n c o u t / set up a d d r c r c 5 e n d p token packet host to device s y n c d a t a 1/0 c r c 16 data data packet host to device setup ack, nak, stal s y n c hand shake packet update device to host 3. out or setup token with crc error s y n c o u t / set up a d d r c r c 5 e n d p token packet host to device s y n c d a t a 1/0 c r c 16 data data packet host to device update only if fifo is written figure 19-5. token/data packet flow diagram
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 44 of 58 20.0 usb mode tables mode this lists the mnemonic given to the different modes that can be set in the endpoint mode register by writing to the lower nibb le (bits 0..3). the bit settings for different modes are covered in the column marked ?mode bits.? the status in and status out represent the status stage in the in or out transfer involving the control endpoint. mode bits these column lists the encoding for different modes by setting bits[3..0] of the endpoint mode register. this modes represents how the sie responds to different tokens sent by the host to an endpoint. for instance, if the mode bits are set to ?0001? (nak in/out), the sie will respond with an ack on receiving a setup token from the host nak on receiving an out token from the host nak on receiving an in token from the host refer to section 13.0 for more information on sie functioning. setup, in, and out these columns shows the sie?s response to the host on receiving a setup, in and out token depending on the mode set in the endpoint mode register. a ?check? on the out token column, implies that on receiving an out token the sie checks to see whether the out packet is of zero length and has a data toggle (dtog) set to ?1.? if the dtog bit is set and the received out packet has zero length, the out is acked to complete the transaction. if either of this condition is not met the sie will respond with a stalll or just ign ore the transaction. a ?tx count? entry in the in column implies that the sie transmit the number of bytes specified in the byte count (bits 3..0 of the endpoint count register) to the host in response to the in token received. note: 4. stall bit is bit 7 of the usb non-control device endpoint mode registers. for more information, refer to section 19.4. table 20-1. usb register mode encoding mode mode bits setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint nak in/out 0001 accept nak nak forced from setup on control endpoint, from modes other than 0000 status out only 0010 accept stall check for control endpoints stall in/out 0011 accept stall stall for control endpoints ignore in/out 0100 accept ignore ignore for control endpoints isochronous out 0101 ignore ignore always for isochronous endpoints status in only 0110 accept tx 0 byte stall for control endpoints isochronous in 0111 ignore tx count ignore for isochronous endpoints nak out 1000 ignore ignore nak is set by sie on an ack from mode 1001 (ack out) ack out(stall [4] =0) ack out(stall [4] =1) 1001 1001 ignore ignore ignore ignore ack stall on issuance of an ack this mode is changed by sie to 1000 (nak out) nak out - status in 1010 accept tx 0 byte nak is set by sie on an ack from mode 1011 (ack out- status in) ack out - status in 1011 accept tx 0 byte ack on issuance of an ack this mode is changed by sie to 1010 (nak out ? status in) nak in 1100 ignore nak ignore is set by sie on an ack from mode 1101 (ack in) ack in(stall [4] =0) ack in(stall [4] =1) 1101 1101 ignore ignore tx count stall ignore ignore on issuance of an ack this mode is changed by sie to 1100 (nak in) nak in ? status out 1110 accept nak check is set by sie on an ack from mode 1111 (ack in ? status out) ack in ? status out 1111 accept tx count check on issuance of an ack this mode is changed by sie to 1110 (nak in ? status out)
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 45 of 58 a ?tx0 byte? entry in the in column implies that the sie transmit a zero length byte packet in response to the in token receive d from the host. an ?ignore? in any of the columns means that the device will not send any handshake tokens (no ack) to the host. an ?accept? in any of the columns means that the device will respond with an ack to a valid setup transaction tot he host. comments some mode bits are automatically changed by the sie in response to certain usb transactions. for example, if the mode bits [3:0] are set to '1111' which is ack in-status out mode as shown in table 19-1 , the sie will change the endpoint mode bits [3:0] to nak in-status out mode (1110) after ack?ing a valid status stage out token. the firmware needs to update the mode for the sie to respond appropriately. see table 18-1 for more details on what modes will be changed by the sie. a disabled endpoint will remain disabled until changed by firmware, and all endpoints reset to the disabled mode (0000). firmware normally enables the endpoint mode after a setconfiguration request. any setup packet to an enabled endpoint with mode set to accept setups will be changed by the sie to 0001 (naking ins and outs). any mode set to accept a setup will send an ack handshake to a valid setup token. the control endpoint has three status bits for identifying the token type received (setup, in, or out), but the endpoint must b e placed in the correct mode to function as such. non-control endpoints should not be placed into modes that accept setups. note that most modes that control transactions involving an ending ack, are changed by the sie to a corresponding mode which naks subsequent packets following the ack. exceptions are modes 1010 and 1110. the response of the sie can be summarized as follows: 1. the sie will only respond to valid transactions, and will ignore non-valid ones. 2. the sie will generate an interrupt when a valid transaction is completed or when the fifo is corrupted. fifo corruption occur s during an out or setup transaction to a valid internal address, that ends with a non-valid crc. 3. an incoming data packet is valid if the count is < endpoint size + 2 (includes crc) and passes all error checking; 4. an in will be ignored by an out configured endpoint and visa versa. 5. the in and out pid status is updated at the end of a transaction. 6. the setup pid status is updated at the beginning of the data packet phase. t able 20-2. decode table for table 20-3 : ?details of modes for differing traffic conditions? properties of incoming packets changes to the internal register made by the sie on receiving an incoming packet from the host interrup t 3 2 1 0 token count buffer dval dtog dval count setup in out ack 3 2 1 0 response int byte count (bits 0..5, figure 17-4) sie?s response to the host endpoint mode encoding data valid (bit 6, figure 17-4) received token (setup/in/out) data0/1 (bit7 figure 17-4) pid status bits (bit[7..5], figure 17-2) endpoint mode bits changed by the sie the validity of the received data the quality status of the dma buffer the number of received bytes acknowledge phase completed legend: tx : transmit uc : unchanged rx : receive tx0 :transmit 0 length packet available for control endpoint only x: don?t care
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 46 of 58 7. the entire endpoint 0 mode register and the count register are locked to cpu writes at the end of any transaction to that endpoint in which an ack is transferred. these registers are only unlocked by a cpu read of the register, which should be done by the firmware only after the transaction is complete. this represents about a 1- s window in which the cpu is locked from register writes to these usb registers. normally the firmware should perform a register read at the beginning of the endpoint isrs to unlock and get the mode register information. the interlock on the mode and count registers ensures that the firmware recognizes the changes that the sie might have made during the previous transaction. note that the setup bit of the mode register is not locked. this means that before writing to the mode register, firmware must first read the register to make sure that the setup bit is not set (which indicates a setup was received, while processing the current usb request). this read will of course unlock the register. so care must be taken not to overwrite the register elsewhere. table 20-3. details of modes for differing traffic conditions (see table 20-2 for the decode legend) setup (if accepting setups) properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr see table 16-1 setup <= 10 data valid updates 1 updates 1 uc uc 1 0 0 0 1 ack yes see table 16-1 setup > 10 junk x updates updates updates 1 uc uc uc nochange ignore yes see table 16-1 setup x junk invalid updates 0 updates 1 uc uc uc nochange ignore yes properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr disabled 0 0 0 0 x x uc x uc uc uc uc uc uc uc nochange ignore no nak in/out 0 0 0 1 out x uc x uc uc uc uc uc 1 uc nochange nak yes 0 0 0 1 in x uc x uc uc uc uc 1 uc uc nochange nak yes ignore in/out 0 1 0 0 out x uc x uc uc uc uc uc uc uc nochange ignore no 0 1 0 0 in x uc x uc uc uc uc uc uc uc nochange ignore no stall in/out 0 0 1 1 out x uc x uc uc uc uc uc 1 uc nochange stall yes 0 0 1 1 in x uc x uc uc uc uc 1 uc uc nochange stall yes control write properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal out/premature status in 1 0 1 1 out <= 10 data valid updates 1 updates uc uc 1 1 1 0 1 0 ack yes 1 0 1 1 out > 10 junk x updates updates updates uc uc 1 uc nochange ignore yes 1 0 1 1 out x junk invalid updates 0 updates uc uc 1 uc nochange ignore yes 1 0 1 1 in x uc x uc uc uc uc 1 uc 1 nochange tx 0 yes nak out/premature status in 1 0 1 0 out <= 10 uc valid uc uc uc uc uc 1 uc nochange nak yes 1 0 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 0 1 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 0 1 0 in x uc x uc uc uc uc 1 uc 1 nochange tx 0 yes status in/extra out 0 1 1 0 out <= 10 uc valid uc uc uc uc uc 1 uc 0 0 1 1 stall yes 0 1 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 0 1 1 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 0 1 1 0 in x uc x uc uc uc uc 1 uc 1 nochange tx 0 yes control read properties of incoming packet changes made by sie to internal registers and mode bits
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 47 of 58 mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal in/premature status out 1 1 1 1 out 2 uc valid 1 1 updates uc uc 1 1 nochange ack yes 1 1 1 1 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 1 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 1 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 1 1 1 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 1 1 1 in x uc x uc uc uc uc 1 uc 1 1 1 1 0 ack (back) yes nak in/premature status out 1 1 1 0 out 2 uc valid 1 1 updates uc uc 1 1 nochange ack yes 1 1 1 0 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 0 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 1 1 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 1 1 0 in x uc x uc uc uc uc 1 uc uc nochange nak yes status out/extra in 0 0 1 0 out 2 uc valid 1 1 updates uc uc 1 1 nochange ack yes 0 0 1 0 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 0 0 1 0 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 0 0 1 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 0 0 1 0 out x uc invalid uc uc uc uc 1 uc uc nochange ignore no 0 0 1 0 in x uc x uc uc uc uc 1 uc uc 0 0 1 1 stall yes out endpoint properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal out/erroneous in 1 0 0 1 out <= 10 data valid updates 1 updates uc uc 1 1 1 0 0 0 ack yes 1 0 0 1 out > 10 junk x updates updates updates uc uc 1 uc nochange ignore yes 1 0 0 1 out x junk invalid updates 0 updates uc uc 1 uc nochange ignore yes 1 0 0 1 in x uc x uc uc uc uc uc uc uc nochange ignore no (stall [4] = 0) 1 0 0 1 in x uc x uc uc uc uc uc uc uc nochange stall no (stall [4] = 1) nak out/erroneous in 1 0 0 0 out <= 10 uc valid uc uc uc uc uc 1 uc nochange nak yes 1 0 0 0 out > 10 uc x uc uc uc uc uc uc uc nochange ignore no 1 0 0 0 out x uc invalid uc uc uc uc uc uc uc nochange ignore no 1 0 0 0 in x uc x uc uc uc uc uc uc uc nochange ignore no isochronous endpoint (out) 0 1 0 1 out x updates updates updates updates updates uc uc 1 1 nochange rx yes 0 1 0 1 in x uc x uc uc uc uc uc uc uc nochange ignore no in endpoint properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal in/erroneous out 1 1 0 1 out x uc x uc uc uc uc uc uc uc nochange ignore no table 20-3. details of modes for differing traffic conditions (see table 20-2 for the decode legend) (continued)
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 48 of 58 (stall [4] = 0) 1 1 0 1 out x uc x uc uc uc uc uc uc uc nochange stall no (stall [4] = 1) 1 1 0 1 in x uc x uc uc uc uc 1 uc 1 1 1 0 0 ack (back) yes nak in/erroneous out 1 1 0 0 out x uc x uc uc uc uc uc uc uc nochange ignore no 1 1 0 0 in x uc x uc uc uc uc 1 uc uc nochange nak yes isochronous endpoint (in) 0 1 1 1 out x uc x uc uc uc uc uc uc uc nochange ignore no 0 1 1 1 in x uc x uc uc uc uc 1 uc uc nochange tx yes 21.0 register summary addr ess register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write /both [5, 6, 7] default/ reset gpio configuration ports 0, 1, 2 and 3 0x00 port 0 data p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 bbbbbbbb 1111111 1 0x01 port 1 data p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 bbbbbbbb 1111111 1 0x02 port 2 data p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 bbbbbbbb 1111111 1 0x03 port 3 data p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 bbbbbbbb 1111111 1 0x04 port 0 interrupt enable p0.7 intr enable p0.6 intr enable p0.5 intr enable p0.4 intr enable p0.3 intr enable p0.2 intr enable p0.1 intr enable p0.0 intr enable wwwwwww w 000000 00 0x05 port 1 interrupt enable p1.7 intr enable p1.6 intr enable p1.5 intr enable p1.4 intr enable reserve d p1.2 intr enable p1.1 intr enable p1.0 intr enable wwwwwww w 000000 00 0x06 port 2 interrupt enable p2.7 intr enable p2.6 intr enable p2.5 intr enable p2.4 intr enable p2.3 intr enable reserve d reserve d reserve d wwwwwww w 000000 00 0x07 port 3 interrupt enable reserve d reserve d reserve d reserve d reserve d reserve d p3.1 intr enable p3.0 intr enable wwwwwww w 000000 00 0x08 gpio configu- ration port 3 config bit 1 port 3 config bit 0 port 2 config bit 1 port 2 config bit 0 port 1 config bit 1 port 1 config bit 0 port 0 config bit 1 port 0 config bit 0 bbbbbbbb 000000 00 hapi i 2 c 0x09 hapi/i 2 c configu- ration i 2 c position reserve d reserve d reserve d reserve d reserve d i 2 c port width reserve d bbbbbbbb 000000 00 endpoint a0, ai and a2 configuration 0x10 usb device address a device address a enable device address a bit 6 device address a bit 5 device address a bit 4 device address a bit 3 device address a bit 2 device address a bit 1 device address a bit 0 bbbbbbbb 000000 00 notes: 5. b: read and write. 6. w: write. 7. r: read. table 20-3. details of modes for differing traffic conditions (see table 20-2 for the decode legend) (continued)
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 49 of 58 endpoint a0, ai and a2 configuration 0x11 ep a0 counter register data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 000000 00 0x12 ep a0 mode register endpoint 0 setup receive d endpoint 0 in receive d endpoint 0 out receive d ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 000000 00 0x13 ep a1 counter register data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 000000 00 0x14 ep a1 mode register stall - - ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 000000 00 0x15 ep a2 counter register data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 000000 00 0x16 ep a2 mode register stall - - ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 000000 00 usb- cs 0x1f usb status and control endpoint size endpoint mode d+ upstrea m d? upstrea m bus activity control bit 2 control bit 1 control bit 0 bbrrbbbb -0xx000 0 interrupt 0x20 global interrupt enable reserve d i 2 c interrupt enable gpio interrupt enable reserve d usb hub interrupt enable 1.024-m s interrupt enable 128- s interrupt enable usb bus reset interrupt enable -bbbbbbb -000000 0 0x21 endpoint interrupt enable reserve d reserve d reserve d epb1 interrupt enable epb0 interrupt enable epa2 interrupt enable epa1 interrupt enable epa0 interrupt enable ---bbbbb ---0000 0 timer 0x24 timer (lsb) timer bit 7 timer bit 6 timer bit 5 timer bit 4 timer bit 3 timer bit 2 timer bit 1 timer bit 0 rrrrrrrr 000000 00 0x25 timer (msb) reserve d reserve d reserve d reserve d timer bit 11 timer bit 10 time bit 9 timer bit 8 ----rrrr ----0000 i 2 c 0x28 i 2 c control and status mstr mode continue / busy xmit mode ack addr arb lost/ restart receive d stop i 2 c enable bbbbbbbb 000000 00 0x29 i 2 c data i 2 c data 7 i 2 c data 6 i 2 c data 5 i 2 c data 4 i 2 c data 3 i 2 c data 2 i 2 c data 1 i 2 c data 0 bbbbbbbb xxxxxxx x endpoint b0, b1 configuration 0x40 usb device address b device address b enable device address b bit 6 device address b bit 5 device address b bit 4 device address b bit 3 device address b bit 2 device address b bit 1 device address b bit 0 bbbbbbbb 000000 00 0x41 ep b0 counter register data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 000000 00 0x42 ep b0 mode register endpoint 0 setup receive d endpoint 0 in receive d endpoint 0 out receive d ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 000000 00 0x43 ep b1 counter register data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 000000 00 0x44 ep b1 mode register stall - - ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 000000 00 21.0 register summary (continued) addr ess register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write /both [5, 6, 7] default/ reset
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 50 of 58 hub port control, status, suspend resume, se0, force low 0x48 hub port connect status reserve d port 7 connect status port 6 connect status port 5 connect status port 4 connect status port 3 connect status port 2 connect status port 1 connect status bbbbbbbb 000000 00 0x49 hub port enable reserve d port 7 enable port 6 enable port 5 enable port 4 enable port 3 enable port 2 enable port 1 enable bbbbbbbb 000000 00 0x4a hub port speed reserve d port 7 speed port 6 speed port 5 speed port 4 speed port 3 speed port 2 speed port 1 speed bbbbbbbb 000000 00 0x4b hub port control (ports 4:1) port 4 control bit 1 port 4 control bit 0 port 3 control bit 1 port 3 control bit 0 port 2 control bit 1 port 2 control bit 0 port 1 control bit 1 port 1 control bit 0 bbbbbbbb 000000 00 0x4c hub port control (ports 7:5) reserve d reserve d port 7 control bit 1 port 7 control bit 0 port 6 control bit 1 port 6 control bit 0 port 5 control bit 1 port 5 control bit 0 --bbbbbb --00000 0 0x4d hub port suspend device remote wakeup port 7 selective suspend port 6 selective suspend port 5 selective suspend port 4 selective suspend port 3 selective suspend port 2 selective suspend port 1 selective suspend bbbbbbbb 000000 00 0x4e hub port resume status reserve d resume 7 resume 6 resume 5 resume 4 resume 3 resume 2 resume 1 -rrrrrrr 000000 00 0x4f hub port se0 status reserve d port 7 se0 status port 6 se0 status port 5 se0 status port 4 se0 status port 3 se0 status port 2 se0 status port 1 se0 status rrrrrrrr 000000 00 0x50 hub ports data reserve d port 7 diff. data port 6 diff. data port 5 diff. data port 4 diff. data port 3 diff. data port 2 diff. data port 1 diff. data rrrrrrrr 000000 00 0x51 hub port force low (ports 4:1) force low d+[4] force low d?[4] force low d+[3] force low d?[3] force low d+[2] force low d?[2] force low d+[1] force low d?[1] bbbbbbbb 000000 00 0x52 hub port force low (ports 7:5) reserve d reserve d force low d+[7] force low d?[7] force low d+[6] force low d?[6] force low d+[5] force low d?[5] --bbbbbb 000000 00 0xff process status & control irq pending wdr usb bus reset interrupt power-o n reset suspend interrupt enable sense reserve d run rbbbbrbb 000100 01 21.0 register summary (continued) addr ess register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write /both [5, 6, 7] default/ reset
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 51 of 58 22.0 sample schematic xtalo xtali d0- d0+ d1+ d1- d2- d2+ d3- d3+ d4- d4+ vcc vref vpp gnd gnd in gnd out usb-b vbus d- d+ gnd .01 uf 6.000 mhz 22x2(r ext ) vbus vref vref .01 uf 2.2 uf 2.2 uf 1.5k shell 10m 4.7nf 250 vac power management usb-a vbus d- d+ gnd usb-a vbus d- d+ gnd usb-a vbus d- d+ gnd usb-a vbus d- d+ gnd 15k(x8) 22x8(r ext ) optional 3.3v regulator (r uup ) (r udn ) figure 22-1. sample schematic
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 52 of 58 23.0 absolute maximum ratings storage temperature ................................. ?65c to +150c ambient temperature with power applied ........ 0c to +70c supply voltage on v cc relative to v ss ........... ?0.5v to +7.0v dc input voltage................................. ?0.5v to +v cc + 0.5v dc voltage applied to outputs in high-z state .................................... ?0.5v to +v cc + 0.5v power dissipation .....................................................500 mw static discharge voltage ..........................................> 2000v latch-up current ................................................... > 200 ma max output sink current into port 0, 1, 2, 3, and dac[1:0] pins ..................................................... 60 ma max output sink current into dac[7:2] pins .............. 10 ma max output source current from port 1, 2, 3, 4 ........ 30 ma 24.0 electrical characteristics electrical characteristics (fosc = 6 mhz; operating temperature = 0 to 70c, v cc = 4.0v to 5.25v) parameter description conditions min. max. unit general v ref reference voltage 3.3v 5% 3.15 3.45 v v pp programming voltage (disabled) ?0.4 0.4 v i cc v cc operating current no gpio source current 50 ma i sb1 supply current?suspend mode 50 a i ref vref operating current no usb traffic [8] 10 ma i il input leakage current any pin 1 a usb interface v di differential input sensitivity | (d+)?(d?) | 0.2 v v cm differential input common mode range 0.8 2.5 v v se single ended receiver threshold 0.8 2.0 v c in transceiver capacitance 20 pf i lo hi-z state data line leakage 0v < v in < 3.3v ?10 10 a r ext external usb series resistor in series with each usb pin 19 21 w r uup external upstream usb pull-up resistor 1.5 k ? 5%, d+ to v reg 1.425 1.575 kw r udn external downstream pull-down resistors 15 k ? 5%, downstream usb pins 14.25 15.75 kw power-on reset t vccs v cc ramp rate linear ramp 0v to v cc [9] 0100ms usb upstream/downstream port v uoh static output high 15 k ? 5% to gnd 2.8 3.6 v v uol static output low 1.5 k ? 5% to v ref 0.3 v z o usb driver output impedance including r ext resistor 28 44 w general purpose i/o (gpio) r up pull-up resistance (typical 14 k ?) 8.0 24.0 k ? v ith input threshold voltage all ports, low to high edge 20% 40% v cc v h input hysteresis voltage all ports, high to low edge 2% 8% v cc notes: 8. add 18 ma per driven usb cable (upstream or downstream). this is based on transitions every two full-speed bit times on avera ge. 9. power-on reset occurs whenever the voltage on v cc is below approximately 2.5v.
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 53 of 58 vol port 0,1,2,3 output low voltage i ol = 3 ma i ol = 8 ma 0.4 2.0 v v v oh output high voltage i oh = 1.9 ma (all ports 0,1,2,3) 2.4 v dac interface r up dac pull-up resistance (typical 14 k ?) 8.0 24.0 k ? i sink0(0) dac[7:2] sink current (0) v out = 2.0v dc 0.1 0.3 ma i sink0(f) dac[7:2] sink current (f) v out = 2.0v dc 0.5 1.5 ma i sink1(0) dac[1:0] sink current (0) v out = 2.0v dc 1.6 4.8 ma i sink1(f) dac[1:0] sink current (f) v out = 2.0v dc 8 24 ma i range programmed isink ratio: max/min v out = 2.0v dc [10] 46 t ratio tracking ratio dac[1:0] to dac[7:2] v out = 2.0v [11] 14 22 i sinkdac dac sink current v out = 2.0v dc 1.6 4.8 ma i lin differential nonlinearity dac port [12] 0.6 lsb 25.0 switching characteristics (f osc = 6.0 mhz) parameter description min. max. unit clock source f osc clock rate 6 0.25% mhz t cyc clock period 166.25 167.08 ns t ch clock high time 0.45 t cyc ns t cl clock low time 0.45 t cyc ns usb full-speed signaling [13] t rfs transition rise time 4 20 ns t ffs transition fall time 4 20 ns t rfmfs rise / fall time matching; (t r /t f ) 90 111 % t dratefs full speed date rate 12 0.25% mb/s dac interface t sink current sink response time 0.8 s hapi read cycle timing t rd read pulse width 15 ns t oed oe low to data valid [14, 15] 40 ns t oez oe high to data high-z [15] 20 ns t oedr oe low to data_ready deasserted [14, 15] 0 60 ns hapi write cycle timing t wr write strobe width 15 ns t dstb data valid to stb high (data set-up time) [15] 5 ns t stbz stb high to data high-z (data hold time) [15] 15 ns t stble stb low to latch_empty deasserted [14, 15] 0 50 ns timer signals t watch wdt period 8.192 14.336 ms notes: 10. irange: i sinkn (15)/ i sinkn (0) for the same pin. 11. t ratio = i sink1 [1:0](n)/i sink 0[7:2](n) for the same n, programmed. 12. i lin measured as largest step size vs. nominal according to measured full scale and zero programmed values. 13. per table 7-6 of revision 1.1 of usb specification. 14. for 25-pf load. 15. assumes chip select cs is asserted (low). electrical characteristics (fosc = 6 mhz; operating temperature = 0 to 70c, v cc = 4.0v to 5.25v) (continued) parameter description conditions min. max. unit
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 54 of 58 clock t cyc t cl t ch figure 25-1. clock timing 90% 10% 90% 10% d ? d + t r t r figure 25-2. usb data signal timing oe (p2.5, input) data (output) stb (p2.4, input) dreadypin (p2.3, output) internal write internal addr port0 d[23:0] t oed t oez t rd t oedr cs (p2.6, input) int (shown for drdy polarity=0) interrupt generated (ready) figure 25-3. hapi read by external interface from usb microcontroller
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 55 of 58 26.0 ordering information ordering code prom size package name package type operating range cy7c66013-pvc 8 kb o48 48-pin (300-mil) ssop commercial cy7c66013-pc 8 kb p25 48-pin (600-mil) pdip commercial CY7C66113-PVC 8 kb o56 56-pin (300-mil) ssop commercial data (input) lemptypin (p2.2, output) internal read internal addr port0 d[23:0] t stble t wr t stbz t dstb oe (p2.5, input) cs (p2.6, input) stb (p2.4, input) (not empty) (shown for lempty polarity=0) int interrupt generated figure 25-4. hapi write by external device to usb microcontroller
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 56 of 58 27.0 package diagrams 48-pin shrunk small outline package o48 51-85061-*c 56-pin shrunk small outline package o56 51-85062-*c
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 57 of 58 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. purchase of i 2 c components from cypress, or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. all product and company names mentioned in this document are the trademarks of their respective holders. 27.0 package diagrams (continued) 51-85020-*a 48-pin (600-mil) molded dip p25
cy7c6601 3 cy7c6611 3 document #: 38-08024 rev. *a page 58 of 58 document history page document title: cy7c66013, cy7c66113 full-speed usb (12 mbps) peripheral controller with integrated hub document number: 38-08024 rev. ecn no. issue date orig. of change description of change ** 114525 3/27/02 dsg change from spec number: 38-00591 to 38-08024 *a 124768 03/20/03 mon added register bit definitions. added default bit state of each register. corrected the schematic (location of the pull-up on d+). added register summary. removed information on the availability of the part in pdip package. modified table 20-1 and provided more explanation regarding locking/unlocking mechanism of the mode register. removed any information regarding the speed detect bit in hub port speed register being set by hardware.

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